🚀 go-pugleaf

In article <ATHEYBEY.89Aug9093829@allspice.lcs.mit.edu> atheybey@lcs.mit.edu (Andrew Heybey) writes:
>In article <120232@sun.Eng.Sun.COM> raz%kilowatt@Sun.COM (Steve -Raz- Berry) writes:
> [I delete my own diatribe in comparing and contrasting DMA vrs polling]
>
>Sounds like a good argument to me.  That said, I've got a GVP and as
>soon as I can scrape together the cash to buy a drive, I'll even have
>it installed :-(.  *If* GVP's software has this hypothetical tight
>loop to transfer data, I should be able to win big by installing a
>68010, no?

The three word instruction loop will definitely help your performance
*if* GVP wrote their software that way. BTW, the 3 bus cycle figure
is more than likely wrong for a plain jane 68K, mainly cause I didn't
figure in the instruction fetches. Probably more like 6 or so.
So for a 68010, you only have to count the data transfers. I'd guess
a bus cycle for data fetch from the drive, and a bus cycle for storing
to the destination memory. You still have some latency waiting for the
CPU to decrement and branch to the start of the loop, but this is still
not too bad.

start:
	move.w (a0),(a1)+	;move data from fifo to destination.
	dbeq   d0,start 	;decrement counter and loop.

That should fit into the three word '010 instruction cache.

Of course you still win bigger with a DMA card.

>Am I all wet?  Has anyone disassembled their GVP driver to find out
>what's going on in there?

I'd be curious to find out too.

---
Steve -Raz- Berry     Disclaimer: It wasn't me! I was volatilizing my esters.
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