Article View: comp.sys.amiga.tech
Article #901Re: DMA or polling (was Re: GVP controller)
From: Checkpoint Technologies
Date: Mon, 14 Aug 1989 19:13
Date: Mon, 14 Aug 1989 19:13
26 lines
1557 bytes
1557 bytes
In article <19160@usc.edu> addison@pollux.usc.edu (Richard Addison) writes:
>In article <63241@linus.UUCP> rachamp@mbunix (Champeaux) writes:
>>The minimum loop required for transferring words from GVP's onboard buffer to
>>main memory is the following:
>>
>>loop: move (a0)+,(a1)+ (24 clock cycles)
>> dbra d0,loop (18 clock cycles)
>
>Try again. This is an obvious way of doing it, but it is not the fastest.
>
>Richard Addison
Well, assuming you have the registers available and the move is
a multiple of 12 longwords, how about this:
loop: movem.l (a0)+,d1-d7/a2-a6
movem.l d1-d7/a2-a6,(a1)+
dbra d0,loop
Won't give you loop mode on the 68010, but it won't matter. You
get 24 words moved for each 6 words of instruction fetch.
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!gatech!uflorida!haven!grebyn!ckp From: ckp@grebyn.com (Checkpoint Technologies) Newsgroups: comp.sys.amiga.tech Subject: Re: DMA or polling (was Re: GVP controller) Message-ID: <12269@grebyn.com> Date: 14 Aug 89 19:13:15 GMT References: <8908092130.AA23369@jade.berkeley.edu> <63241@linus.UUCP> <19160@usc.edu> Reply-To: ckp@grebyn.UUCP (Checkpoint Technologies) Organization: Grebyn Corp., Vienna, VA, USA Lines: 26