🚀 go-pugleaf

In article <7476@cit-vax.Caltech.Edu> stevel@tybalt.caltech.edu (Steve Ludtke) writes:
> 
> Hi. I've been playing around with the XCLK outputs on the 23 pin
> video output, and there are a few things I can't find in the hardware
> manual. Supposedly, pin 1 (XCLK) will change state whenever the background
> color (color 0) is being displayed. The XCLKEN (pin 2) and GNDRTN (pin 13)
> are what I don't understand. XCLKEN is supposed to be an active low pin.
> I assumed it was an input, and brought it low. That caused the display
> to go blank, and I had to reset to get it back. Now I'm trying to figure
> out what exactly this pin is. Is it a sync pulse input for genlocking,
> an output indicating whether XCLK is enabled/disabled, or something
> else ? (by the way, I get a constant high output from XCLK, ie no 
> low pulses for bkgnd color.) Any help would be greatly appreciated.

You're some confused.  XCLK is an alternate 28 MHz system clock input
for genlock applications.  _XCLKEN is a low active signal that selects
the XCLK signal vs. the internal oscillator.  It's not meant to be
switched on a dynamic basis.

What you seem to be looking for is the ZD pin, which is an output
that is driven low when the video being display is effectivly
"color 0".  This can be used by an external device to switch beteen
the "background" Amiga video and some other video source.

In "genlock mode" the software senses that some external sync signal
is being applied to the HSYNC and VSYNC outputs and sets a bit that
redefines them as horizontal and vertical "reset" signals.  Due to
implementation details these resets must be supplied every other
field and every other line - thus the H/2 and V/2 designations...

-- 
George Robbins - now working for,	uucp: {uunet|ihnp4|rutgers}!cbmvax!grr
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