🚀 go-pugleaf

elendir@inf.enst.fr writes:

> Stig Vidar Hovland writes
> 
> ] Mr. Joern Moe has probably circuit diagrams for the Falcon and in that case
> ] he should know what he is talking aboat. With additional hardware, it is  
> possible
> ] to terminate an access to 16 bit memory with STERM.

>  Of course with additionnal hardware you can do everything. But I remember  
> something in the developer documentation (v 0.3, July  92) speaking of wait  
> states...
>  Anyhow, a 32 bit synchronous access in 4 cycles has 2 wait states in it. And  
> that, you cannot discuss it :-)

Well if you are making "a 32 bit synchronous access in 4 cycles" on a 16 bit 
bus there can be NO WAIT STATES. To get 32 bits you must make two 16 bit 
accesses. Since each access requires 2 clock cycles, two accesses require 
4 clock cycles.

I think what you meant is that 4 clock cycles, to access 32bits, on a
16 bit bus is the equivalent of 2 wait states on a 32 bit bus.


Brian, WS1S (ST/TT user)
Bell Northern Research
Research Triangle Park, NC