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In article <4044@sdcsvax.UCSD.EDU> mr-frog@amos.UUCP (Dave Pare) writes:
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| > Second, One of the hallmarks of a true-blue RISC chip, however, is
| > *LOTS* of registers.  The Am29000, for instance, has 192.  Only large
| > structs and arrays need to go off-chip.
| 
| Is this per-context, or are they shared between all the running processes?
| After all, the transputer is not a single-process machine!
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There exist two "models" of register usage -- the stack cache model and
the register bank model.  In the stack cache model, each process uses
the entire register file (the local registers are used as a scalar stack
cache) and the registers must be saved on context switches.  In the
register bank model, the registers are divided up into 8 banks of 16
registers apiece, so up to 8 processes can be "resident".  Our initial
software will only support the stack cache model, however.

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| As I understand it, RISC machines have difficulties once the number
| of runnable processes gets above the number of "hardware" contexts
| available to it.  I think that if you have a task that fires off 30
| processes, the transputer will blow the doors off anything else,
| because its switching overhead is 10% of most other machines.
| What is the switch time of the Am29000?
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For the stack cache model, the state can be saved in around 120-150
cycles (assuming single-cycle burst-write memory), which is between 4.8
and 6 microseconds.  It takes a like amount of time to reload a new
context.  For the register bank model, the task switch can occur in
about 20 cycles (800 ns).

Yes, the transputer has a low context-switch time, but if you are really
switching that often that 4 microseconds makes a difference, you
probably aren't getting much work done, anyway.  Note that most UNIX
machines perform roughly 60 - 100 context switches per second, so that
register-save time is in the noise.

	-- Tim Olson
	Advanced Micro Devices
	(tim@amdcad.amd.com)