🚀 go-pugleaf

In article <SCP.90Feb16092214@blanche.LANL>GOV> scp@acl.lanl.gov writes:
:
:Someone wrote me:
:> Stephen,
:
:>        Do you have a description of the 500 architecture
:> (instructions, timing, pipelines, etc.)?  We have been unable to dig
:> one out of our local people, but we haven't pressed the issue yet.  An
:> instruction set manual would have been very helpful in locking down
:> the compiler bug that zapped Perl, besides the inherent educational value.
:> As it is, I'm guessing at the mnemonics that I get out of the debugger.
:
:>        If you have been able to get such a manual (which I presume
:> you'd need to port gcc), that might give us some leverage with the locals.
:
:
:I haven't had much more luck.  All I have been able to get on this subject
:is a handwritten ``wall chart'' that is nearly illegible.  It shows the
:opcode <-> mnemonic mappings, with the explaination of the mnemonic
:(like ``djibzm'' == ``delayed jump on indicator bit pairs zeros minus'',
:stephen pope
:advanced computing lab, lanl
:scp@acl.lanl.gov
:
:ps.  yes, I know that two copies of my postings seem to escape.
:Fixed Real Soon Now.

I think the celerity uses the NCR/32 VLSI CPU chip.  I have in my
hands the _NCR/32 General Information Manual_ (c)1984 (ST-2104-23)
and it does have a one page description of djibzm.  I think you'll
find it explains everything in adequate detail.

There's an 800 number on the back:

NCR VLSI Processor Products
NCR Microelectronics Division
Colorado Springs, Colorado
(800)525-2252

Good luck!


-- 

Dan Mercer
Reply-To: mercer@ncrcce.StPaul.NCR.COM (Dan Mercer)