🚀 go-pugleaf

Marissa,

  Here's the best update I can make you on the internal structures of the
DS5000/240 (I haven't forgotten your request on the I/O CTL specification 
either, I'm trying to get as many of the ASIC interfaces as I can through
a DEC legal review...might as well be shot for a sheep as a lamb). Here's
my breakdown:


For those of you who are unfamiliar with the abbreviations that Marissa used:

MB	Memory Buffer ASIC	Provides the new write buffer functionality.

MT	Memory Turbo ASIC	Provides the memory controller and also the
				TURBOchannel master.

MS	Memory Strobe ASIC	Provides a gated clock signal to the memory
				module being addressed (note that this is 
				different from the DS5000/200 which did clock
				distribution to all memory slots every cycle.

Your note is quite accurate as it stands.  Here's some more data:

CPU             <->     cache system            : non-multiplexed, shared w/MB
CPU/cache       <->     "MB" ASIC               : non-multiplexed
"MB" ASIC       <->     "MT" ASIC               : non-multiplexed
"MT" ASIC       <->     "MS" ASIC               : not a bus
"MS" ASIC       <->     system memory modules   : not a bus

The MB and cache share the same non-multiplexed address and data busses
from the R3000, running at 40+ Mhz.  The connection between the MB and MT
is also a non-multiplexed interface with separate address and data busses,
running at <= 25 Mhz.  The MT then sprouts 4 busses:
        Memory DRAM address bus (10 bits)
        Memory data/ecc lo bus (39 bits)
        Memory data/ecc hi bus (39 bits)
        Multiplexed TURBOchannel address/data bus (32 bits)


I hope this gives you sufficient help.

				Thanx,
				  AJ


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