🚀 go-pugleaf

In article <1992Dec31.164221.27734@aplcen.apl.jhu.edu> shif@aplpy.jhuapl.edu (Gary D. Shiflett) writes:
>Malak was interested in comparing the i860 FFT performance to other 
>commercially available DSPs. My question is: what is the FFT performance of
>the family of DEC alpha micros (theoretical, simulated, or measured ???)?
>I would be interested in knowing not only MFlops, but also FFT algorithm,
>transform size(s), optimum execution times, and any stipulations (as
>described by Alan above) associated with the benchmarks.

For a 1024 point, complex, single precision FFT (i.e. just fits in the on-chip
8K D cache), we have a measured time of 96,000 cycles.  For the various Alpha
systems, this translates to:

	133 MHz clock		722 microseconds
	150 Mhz			640 microseconds
	200 MHz			480 microseconds

The algorithm is a radix-4 algorithm, and is basically just a C translation
of the FORTRAN code in "DFT/FFT and Convolution Algorithms" by Burrus and 
Parks (with a few tweaks, of course).  It was compiled with GCC 2.3 and
the execution time was measured with the Alpha's process cycle counter.

The Digital Extended Math Library (DXML) for Alpha reportedly can do even 
better, but I don't have any current performance numbers.  For more info on
DXML, contact your local Digital sales rep.

For some more information on signal processing on Alpha, see our technical
report "Are DSP Chips Obsolete?" available via anonymous FTP from 

	crl.dec.com:/pub/DEC/CRL/tech-reports/92.10.ps.Z

For details on e-mail retrieval, or ordering printed copies, send a message
with a "help" subject to:

	techreports@crl.dec.com

If you have any other Alpha questions, feel free to drop me a note.
-- 
Andrew C. Payne
DEC Cambridge Research Lab