🚀 go-pugleaf

In article <2056@gluteus.ai.mit.edu> cracraft@wheaties.ai.mit.edu (Stuart Cracraft) writes:
>
>After benchmarking the new 3100 with a C dhrystone program
>(25,000 dhrystones per second), I felt it would probably
>do pretty well on an application, since a VAX 8810 scored
>8,333 dhrystones per second with the same C program.
>
>Imagine my surprise when the application ran only marginally
>faster on the 3100 (unloaded) than on the 8810!
>
>Do you think (dare say) these machines are optimized for
>the typical benchmarks?
>
>	Stuart

You must remember that just because a processor does some things
well, it doesn't do everything well.  There are several potential problems
with the Rxxxx series such as the MMU.  Whenever the address translation 
unit misses, a trap is taken and SOFTWARE has to reload the TLB.  This 
can take a large amount of time away from applications if memory access 
patterns are sufficiently random.  Dhrystone is quite localized so this
will not normally be seen there.  Also, I have noticed that MIPS has 
some of the most sophisticated optimizing compilers around yet if you 
run another RISC at the same speed (such as the 88K), the MIPS looses 
in the dhrystones race.  There is something non-obvious about predicting 
the performance of MIPS based machines in general which I don't know about. 

As for the general case of RISCs versus CISCs, I can say that my experience
with the 88K products (AViiON in particular) tells me that for most 
applications a RISC will substantially outperform a CISC.  We have noticed
that DG/UX runs MUCH better on a multiple processor 88K than it does on
a Dual MV20000.

It is possible to optimize architectures and compilers for certain 
benchmarks, but this almost always gets caught.  Independent benchers
will usually change around the standard benchmarks enough to fool 
special recognition routines in the compilers.

Robert Cousins
Dept. Mgr, Workstation Dev't
Data General

Speaking for myself alone.