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Article #5614

Re: Digital Review SBC article

#5614
From: Bruce Wright
Date: Sat, 10 Feb 1990 20:35
34 lines
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In article <26668@cup.portal.com>, cliffhanger@cup.portal.com (Cliff C Heyer) writes:
> Re:  Digital Review 1/29/90  P. 1 
> "DEC Set For Move into Board Level Market"
> 
> [...]
>
> Also note the new SBC uses the MicroVAX II 78032 
> chip (not the MV 3000 78034) which on the MicroVAX 
> II only had 1 MIPS at 20MHz(Digital Review 9/85 p. 
> 60), now suddenly it has 4.8 MIPS at 20MHz in the 
> new SBC product. What goes? If the chips are the 
> same I must conclude VMS does not give a single job 
> full uP MIPS, which is what I always suspected.

I don't know what the exact configuration of the new board-level machine
is, so I can't really say whether the 4.8 MIPS at 20MHz is a realistic
figure.

But you should be aware that the standard MicroVAX II configuration
does not have ANY cache memory.  That's one of the major enhancements
of the MicroVAX III line (not only does the chip have some built-in
cache on the III, but some of the models also have additional cache).

It would be quite possible for DEC to boost performance fairly cheaply
by adding a cache to the board-level product.  Anybody know if this is
what they in fact did?

The comment about VMS is rather silly - yes, machines that run it are
much more expensive than lots of other machines, but its speed on a
MicroVAX isn't really that different from, for example, Ultrix.  The
bottom line is that a MicroVAX II just isn't that fast, at least as
it's usually configured.

						Bruce C. Wright
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From: bcw@rti.UUCP (Bruce Wright)
Newsgroups: comp.sys.dec
Subject: Re: Digital Review SBC article
Summary: Processor speeds
Message-ID: <3547@rti.UUCP>
Date: 10 Feb 90 20:35:01 GMT
References: <26668@cup.portal.com>
Organization: Research Triangle Institute, RTP, NC
Lines: 34