🚀 go-pugleaf

Re: PDP-11 MOVB instruction

Standard PDP-11 interface design is such that the decoding of the bus signals 
will generate either a BYTE write OR a WORD write signal. There is a specific 
signal for this: BWTBT. "It is asserted during BDOUT (in a DATOB bus cycle) 
for byte addressing." (DEC specifications.) The best place to see this is in
the DRV-11 circuit diagrams, or in the DCK chip specifications. If you do it
any other way, that's your decision, and NOT in accord with the PDP-11
architecture. 

The suggestion that most cases would "sign-extend" is not correct. In fact, 
apart from the MOVB #-1,R0 case (register destination), I am unaware of any 
cases where this has been seen.

At one stage, DEC had an application note giving detailed information on how 
to use the DCK set: if you are interested your sales rep might be able to dig 
up a copy. Well, he's got to be useful for SOMETHING!?


PS: Note that the DRV11 is NOT compatible with the Q-bus specifications is 
implemented on the uVAX II. The DCK chip set is compatible however, as is the
DRV11-J quad version. There is a small mod you can do to the DRV11 to make it 
work, but it is a bit non-standard!

Alternately, you can just put the DRV11 in, wait for a bus crash/bug check due
to failure to conform to Q-bus specifications, and then tell the system to
continue! This leaves the bus-error flip-flop set, but the bus interface
controller is edge sensitive and fails to see this anymore .... You won't
detect any other bus failures either, which could be a problem .....

Needless to say, DEC don't want to know about such devious mistreatment of the
system, and I certainly don't accept any responsibility either!

My thanks to Eric Piip of DEC Australia for the technical information which 
sorted this gremlin out for me. The info Is available on the internal network, 
somewhere!