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Article #18905Re: Why does my 486 require 2 wait states?
From: Thomas D. Barrett
Date: Tue, 05 Jan 1993 15:13
Date: Tue, 05 Jan 1993 15:13
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In article <1993Jan4.213815.28624@bmers95.bnr.ca> khor@bnr.ca writes: > With 33MHz, you are accessing the memory at (1/33E6)secs = 30.3 ns. > That is too fast as most DRAMs can only provide access reliablity > of 70/80ns (older DRAMs -> 100ns). Actually it isn't so bad... 60ns DRAM have a page mode access of 30ns, Since the 0ws cycle has about 40ns of time available, it is possible that some designs might try for 0ws page mode (although 1ws is more realistic). Using interleaved memory and burst mode (486) it is possible to do the x-2-2-2 cycles without much difficulty. -- |Tom Barrett (TDBear), Sr. Engineer|tom.barrett@amd.com|v:512-462-6856 | |AMD PCD MS-520 | 5900 E. Ben White|Austin, TX 78741 |f:512-462-5155 | |"No is yes, And we're all free" |CO made a #2 no-no... PU! | |My views are my own and may not be the same as the company of origin |
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Path: arc1-ca.pugleaf.net!sparky!uunet!olivea!veritas!amdcad!dvorak.amd.com!tdbear From: tdbear@dvorak.amd.com (Thomas D. Barrett) Newsgroups: comp.sys.ibm.pc.hardware Subject: Re: Why does my 486 require 2 wait states? Message-ID: <1993Jan5.151349.14171@dvorak.amd.com> Date: 5 Jan 93 15:13:49 GMT References: <1ia62bINN37o@savoy.cc.williams.edu> <1993Jan4.213815.28624@bmers95.bnr.ca> Organization: Advanced Micro Devices, Inc.; Austin, Texas Lines: 17