🚀 go-pugleaf

In article <1993Jan5.152504.9786@bmers95.bnr.ca> khor@bnr.ca writes:
>Don't think in terms of 2 distinct stages of testing - at 33MHz and at
>25MHz. It is all one stage.   Depending on the test, it could be a
>single test that grades accoringly.
> 
	Exactly.  Picture drawing a graph for each chip with voltage on the
x axis and frequency on the y axis.  There is a guaranteed working domain
on this graph for this chip.  The testers (which are pretty complicated 
beasts by the way, each one  costing over a million bucks), change both
the voltage and frequency in steps while running test vectors through the
chips, and thus cover the entire domain where the chip is guaranteed.  
The data from this tests will tell which "bin" the chip will go into.  The
typical convention is that Bin 1 is All tests pass at high speed, Bin
2 is All tests pass at some lower speed, and so on.  Then come bins that 
indicate some specific failure mode, random bit fails, or stuck-at faults,
or shorts, or opens, and so on.

-- 
Sam Sivakumar		    |  Intel's very own lithography dude, 
ssivakum@ptdcs5.intel.com   |  Speakin' for himself, that's for sure!
PTD, Aloha, OR              |