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Article #18968

Dynamic RAM

#18968
From: Nic Percival (x5336)
Date: Thu, 21 Jan 1993 11:45
35 lines
2508 bytes
There's been a lot of stuff on this newsgroup recently about clock cycles
etc required by 33MHz or whatever processor accessing say 70ns memory.
The assumption in all of these is that a processor with say a 20ns (50MHz)
clock will have to wait 4 clock cycles to access 70ns memory. If this
is correct then I guess PCs must employ page mode access of dynamic memory.
When I were a lad, back in the mid-80s, the access time specified on a
dynamic memory chip (lets say 150ns) was the RAS (row address select) time.
The address was (and I'm certain still is)clocked into the chip in two
halves, by RAS and CAS (column address select). The data (in a read )
would only appear on data lines some time after the CAS signal became
active. Now what I'm getting at thru all of this was the old 150ns 64K
DRAM chips actually had a full access time of about 260ns. The only way
this could be improved was if accessing a bit in the same row as the last
bit accessed, RAS could be left active, CAS made inactive, column address
changed, CAS made active. This I believe is page mode access. However
it can't be used all the time 'cos you sometimes want to use a different
row in the chip.
Is all this stuff now dealt with by memory management hardware? i.e if
row address changes during CPU execution of a program, does the MMU slap
waits on the CPU until it can get data required?? Or are all of those guys
saying '70ns memory with 20ns cpu cycle will take 4 clock cycles' talking
bollocks?.
One further point. As I said memory access time specified on a chip used
to be RAS time, and I think probably still is. As I recall (and if
I'm remembering a TI data sheet I haven't seen in 4 years correctly)
page mode memory access time is somewhat less than RAS time, so perhaps
a 70ns chip being page mode accessed could be run at 3 cycles per access?

Cheers,
-- 
  Nic Percival      |                               |
  Micro Focus       | "Anything is good and useful  |   nmp@mfltd.co.uk
  Newbury           |  if it's made of chocolate.." |   (0635) 32646 Ext 5336 
  Berks, RG13 1JT   |                               |
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Message-ID: <1993Jan21.114541.1191@mfltd.co.uk>
Path: arc1-ca.pugleaf.net!sparky!uunet!pipex!mfmail!nmp

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Newsgroups: comp.sys.ibm.pc.hardware
Path: arc1-ca.pugleaf.net!sparky!uunet!pipex!mfmail!nmp
From: nmp@mfltd.co.uk (Nic Percival (x5336))
Subject: Dynamic RAM
Message-ID: <1993Jan21.114541.1191@mfltd.co.uk>
Sender: nmp@mfltd.co.uk (Nic Percival (x5336))
Reply-To: nmp@mfltd.co.uk
Organization: Micro Focus Ltd, Newbury, England
Date: Thu, 21 Jan 1993 11:45:41 GMT
Lines: 35