🚀 go-pugleaf

In article <C18y4y.6rx@inews.Intel.COM> ttung@td2cad.intel.com (Thye-Lai Tung) writes:
>There is no interleave, but luckily, the cache system can cover up
>the problem somewhat. Doesn't that sound stupid anyway !

It depends on the memory arch and speed... 0ws page mode is quite
possible.  But, with two levels of cache (one or both being
write-back and one being 256K or larger), the very few misses do
indeed not make a big difference.  Especially to the folks who still
think Landmark SPEED is a good *system* benchmark.

>I find
>36-bit modules more flexible and suitable for 386DX and 486. But they are
>not widely used in clone systems, why ?

Customer demand... and I wouldn't say that 1M SIMMs are very flexible.
Until the 1Mx4 parts became available, it was hard to explain to folks
that they couldn't get beyond 8M in their system when other people
with 8-slots could get 32M.  There were a few companies with the x36
arch and who had 64-bit and 128-bit memory... again, it was a hard
sell.

>Theory aside, how do 16M, one-bank machines fare in real life with real
>applications ?

It's cheaper to throw a DX2 at the problem or add 16 more MBytes.

-- 
|Tom Barrett (TDBear), Sr. Engineer|tom.barrett@amd.com|v:512-462-6856 |
|AMD PCD MS-520 | 5900 E. Ben White|Austin, TX  78741  |f:512-462-5155 |
|"No is yes, And we're all free" ---Tracy Chapman, "Why?"              |
|My views are my own and may not be the same as the company of origin  |