🚀 go-pugleaf

In article <C18uoH.7GA@undergrad.math.waterloo.edu> ychung@cayley.uwaterloo.ca (Young Chung) writes:
>In article <1993Jan21.112136.2125@dmu.ac.uk> cph@dmu.ac.uk (Chris Hand) writes:
>>
>>People have been talking about the BIOS making a difference to the refresh,
>>but I would have thought it's the CHIPSET we should be looking at?  After
>>all that's what controls the refresh, caching etc.
>>
>Well, I don't have the manuals with me to give any specifics about my 
>machine, but I think the 3-chip parity problem is caused by the BIOS
>incompatibility.
>
>This is what happened to me.
>
>I had 4Meg of 9-chip simms and bought 4 more 3-chip simms.  I installed it
>with ease and boot up.  The computer would tick for 4Megs then hangup.
>CMOS chipset error!  So, I turned off the above 1 meg memory check off and
>no problem.  I then proceded to windows and decided to use all 8megs of
>memory.  So I open up a BIG TGA file.  Parity error in the middle of loading.
>So I put the 3-chip simms on the first bank (making them the first 4 megs).
>Now, CMOS error occurs as soon as it starts memory test.  So I turn parity
>check off in my BIOS setup.  Now, it runs with no problem.  Windows gave me
>no trouble.  Of course, when I installed OS/2 2.0, I stated getting that
>parity error again.  
>But, my point is that since I was able to fix the problem, at least temporarily,
>I believe that it's the BIOS that causes 3-chip simm incompatibility.
>
>AMI Feb/91 (I think).
>
>
>----------
>Young :-) ychung@napier.uwaterloo.ca  3@#j3kdi$#%98sk30dskf@#sd.as..3k/sdf3lkdf
> ......##,3@!!!,#@##?P}{ -- I'm a .signature Virus!! --.
>
>

Well, I've got 4MB of 3 chip simms, and 4MB of 9 chip.
Haven't had a problem from day 1.

Environment:
	Clone Motherboard
	ETEQ Chipset
	AMI Hi-Flex Bios dated 5/5/91

Relevant settings:
	Concurrent Refresh:		Disabled
	Page Interleave:		Enabled
	DRAM Write wait state:		2W/S
	DRAM Read wait state:		3W/S
	RAS* Timeout mode counter:	Disabled
	Page mode:			Enabled
	Post write control:		Disabled
	CAS Pulse width:		3 CLK2
	RAS Precharge time:		6 CLK2
	RAS to CAS delay:		2 SYSCLK

----
Mark Bergman    (Biker, Stagehand, (former) Unix user support grunt)
718-855-9148

bergman@panix.com
{cmcl2,uunet}!panix!bergman