🚀 go-pugleaf

In article <2137@acf5.NYU.EDU> liuyu@acf5.NYU.EDU (liuyu) writes:
>ronaldm@rgm.com (Ronald Mendoza) writes:
>
> >I have a 486DX-50 and was looking at the Hidden Refresh option in the CMOS.
> >(AMI BIOS)  Well, it defaults to Disabled, but I recall reading that it should
> >be enabled for 3 chip 1M, or any 4M.  SO, I Enabled the setting since I have
> >(4) 4Mx9 9-chip (do 3-chip exist?) and (4) 1Mx9 3-chip.  Now, my 3D Bench
> >rating went from 37 fps to 40 fps.  Is everything set correctly now?
> 
> >-Ron (ronaldm@rgm.com)
>
>Can you enlighten us where the hidden refresh option is?  I also have AMI
>BIOS (12/12/91).
On my 386 AMI BIOS (2/90 or 24Dec90, depending on whose date you count
:) ) it is called "Concurrent Refresh" (No relation... ) vs. "AT Style
Refresh".

My default was "Concurrent Refresh" and that worked fine with 1Mx9 9
chip SIMMS. When I added some 1Mx9 3 chip SIMMS, the world fell apart!
By setting "AT Style Refresh" sanity was restored.

It was suggested to me that this setting affects how many address lines
get refreshed, and that the BIOS KNOWS that it needs to refresh all of
them for 4Mx9 SIMMS, but doesn't recognise that it needs to do so for the
newer 3 chip 1Mx9 SIMMS (hence you have to tell it...).

I found that when the settings were wrong, and I had "parity checking"
enabled, that I got lots of parity errors - which got worse as the
machine warmed up. Windows 3.1 wasn't terribly happy either....

That is what I found, anyway....

Neil

-- 
Neil Watson, ESDG Product Support, Concurrent Computer Corp
G0BLD        227 Bath Road, Slough, Berks, SL1 4AX, England
             Phone: (+44) 753 513360  FAX: (+44) 753 513303 
(nnw@slough.ccur.com, nnw@concurrent.co.uk or 100021,3041 @ Compuserve)