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Article View: comp.sys.ibm.pc.misc
Article #1168

Memory interleave and page mode with Headland chipset

#1168
From: Bengt Ask
Date: Sun, 16 Aug 1992 14:28
32 lines
2110 bytes
I have a 33 MHz 386SX with a Headland HT-18C chipset and
8 MB of memory (8*1MB SIMMs) in four banks. The manual only
speaks in general terms, but says the chipset supports page
mode and 2-way interleaving, and 4 bank 4-way interleave mode.

  * Does the chipset automatically use the best interleave
    mode depending on the number of banks? There is no entry
    in the setup to control this.
  * Since I know my SIMMs support page mode operation, is it likely
    that this feature is actually used? As with the interleave, there
    is no way to enable the function manually. BTW, almost all DRAM
    chips I have come across do, according to the data sheets, support
    page mode operation, so page mode operation shouldn't be very
    exotic.
  * Sometimes the Landmark v. 2.0 test shows a speed rating of
    41 MHz, and sometimes, depending on where in memory the Landmark test 
    is loaded, it drops to 30 MHz. Similarly, PC Tools 5.0 speed rating is
    sometimes 1460% and sometimes 1660% (of the original PC:s speed). 
    Is this an effect of interleave or page mode operation?
  * Although a 66 MHz X-tal is used, all programs (Checkit and others)
    report a clock speed of only 31.8 MHz. I have actually measured
    the frequency at the clock input of the CPU, and it IS only about 
    63.7 MHz. Why is it so and is this a normal behavior? In the 
    "non-turbo" 8.25 MHz mode, the clock input is exactly 16.5 MHz,
    which is what one would expect.

If anyone has Headland's fax number, could you pass it
on to me?

Please email any replies.

  Bengt Ask, Lund Institute of Technology, Lund, Sweden
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From: f89ba@efd.lth.se (Bengt Ask)
Newsgroups: comp.sys.ibm.pc.misc
Subject: Memory interleave and page mode with Headland chipset
Message-ID: <1992Aug16.142818.10378@lth.se>
Date: 16 Aug 92 14:28:18 GMT
Sender: newsuser@lth.se (LTH network news server)
Organization: Lund Institute of Technology, Sweden
Lines: 32