🚀 go-pugleaf

>A word of warning--don't expect the 586 to give a  factor of 10 improvement 
>in speed over a 486.  Intel likes to quote peak numbers, and, if memory
>serves, the 586 gets a lot of its performance by having multiple units
>(e.g. floating-point, integer, branching, etc) on the chip that can
>execute simultaneously; it can  perform more than one instruction per
>clock cycle, under the right circumstances.  In practice, compilers will 
>virtually *never* be able to generate code that causes *all* the units to 
>execute at once.  My RS6000 can in principle execute 4 or 5 instructions
>simultaneously;  in practice it seems to do 1.5-2.  I guess I'd
>expect the 586 to give maybe a little more speedup than the factor
>of 3 quoted for the 386-486 comparison, but not the factor of 10 you'd
>guess based on a comparison of the 486 vs 586 MIPS.  Wait for some
>real-world benchmarks before you get too excited.

You have some good points but you don't understand the architecture of
the p5.  Code is not required to be recompiled to run on the two
integer units.  Instructions will execute simultaneously *except* for
a very limited set of circumstances.  They will probably achieve a CPI
very close to 2.  Now, in order to take advantage of the vectorized fp
unit you *will* have to recompile.  If you don't recompile Intel is
still saying that you should see a factor of at least 4 speedup in the
fp instructions.

You're right, a factor of 10 is too generous
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