Article View: comp.sys.ibm.pc
Article #14379FAQ serial port (part one)
From: Christian Blum
Date: Mon, 25 Jan 1993 10:03
Date: Mon, 25 Jan 1993 10:03
757 lines
34115 bytes
34115 bytes
This is a FAQ answer on serial communications using the TTY protocol. It
contains information on the TTY protocol and hardware and software implemen-
tations on IBM PCs which is derived from National Semiconductor data sheets
and practical experience of the author and his supporters.
If you want to contribute to this FAQ in any way, please email me (probably
by replying to this posting). My email address is: chbl@stud.uni-sb.de
See the end for details.
It's the second publication of this file. Lots of errors have been
removed, and lots of information has been added (which has surely brought
other errors with it, see Murphy's Law).
PART ONE - HARDWARE & SOFTWARE
Acknowledgements
================
The following persons have contributed (directly or indirectly :-) to this
summary:
Madis Kaal <mast@anubis.kbfi.ee ??> this address is known to be bad
Steve Poulsen <stevep@ims.com>
Scott C. Sadow <NS16550A@mycro.UUCP>
Dan Norstedt <?>
[Commercial: This line could display YOUR name!]
Introduction
============
One of the most universal parts of the PC is its serial port. You can
connect a mouse, a modem, a printer, a plotter, another PC, ...
But its usage (both software and hardware) is one of the best-kept secrets
for most users, besides that it is not difficult to understand how to
connect (not plug-in) devices to it and how to program it.
Regard this FAQ as a manual of the serial port of your PC for both
hardware and software.
Historical summary
------------------
In early days of telecommunications, errand-boys and optical signals (flags,
lights, clouds of smoke) were the only methods of transmitting information
across long distances. With increasing requirements on speed and growing
amount of information, more practical methods were developed. One milestone
was the first wire-bound transmission on May 24th, 1844 ("What hath God
wrought", using the famous Morse-alphabet). Well, technology improved a bit,
and soon there were machines that could be used like typewriters, except that
you typed not only on your own piece of paper but also on somebody elses.
The only thing that has changed on the step from the teletyper to your PC
is speed.
The TTY (teletyping) protocol
-----------------------------
Definition: A protocol is a clear description of the LOGICAL method of
transmitting information. This does NOT include physical realisation.
The TTYp uses two different states of the line called 'mark' and 'space'.
If no data is transmitted, the line is in the 'space' state. Data looks
like
space ----------+ +-------+ +---+ +-------
| | | | | |
mark +---+ +---+ +---+
(1) --------(2)-------- (3)
(1) start bit (2) data bits (3) stop bit(s)
Both transmitter (TX) and receiver (RX) use the same data rate (measured
in baud, which is the reciprocal value of the smallest time interval between
two changes of the line state. TX and RX know about the number of data
bits (probably with a parity bit added), and both know about the size of
the stop step (called the stop bit or the stop bits, depending on the size
of the stop step; normally 1, 1.5 or 2 times the size of a data bit). Data
is transmitted bit-synchroneously and word-asynchroneously, which means that
the size of the bits, the length of the word etc.pp. is clearly defined
but the time between two words is undefined.
The start bit indicates the beginning of a new data word. It is used to
synchronize transmitter and receiver.
Data is transmitted LSB to MSB, which means that the least significant
bit (Bit 0) is transmitted first with 4 to 7 bits of data following, re-
sulting in 5 to 8 bits of data. A logical '0' is transmitted by the
'space' state of the line, a logical '1' by 'mark'.
A parity bit can be added to the data bits to allow error detection.
There are two (well, actually five) kinds of parity: odd and even (plus
none, mark and space). Odd parity means that the number of 'mark' steps in
the data word (including parity bit) is always odd, so the parity bit is
set accordingly (I don't have to explain 'even' parity, must I?). It is
also possible to set the parity bit to a fixed state or to omit it.
The stop bit does not indicate the end of the word (as it could be
derived from its name); it rather separates two consecutive words by
putting the line into the 'space' state for a minimum time.
The protocol is usually described by a sequence of numbers and letters,
e.g. 8n1 means 1 start bit (always), 8 bits of data, no parity bit, 1 stop
bit. 7e2 would indicate 7 bits of data, even parity, 2 stop bits (but I've
never seen this one...). The usual thing is 8n1 or 7e1.
Early teletypers used the neckbreaking speed of 50 baud (which means
that one step is 20ms), 5 bits of data, no parity and 1.5 stop bits (don't
ask me why!). Your PC is capable of serial transmission at up to 115,200
baud (step size of 8.68 microseconds!). Typical rates are 300 baud, 1200 baud,
2400 baud and 9600 baud.
The physical transmission
-------------------------
Teletypers used a closed-loop line with a space current of 20ma and a
mark current of 0ma (typical), which allowed to detect a 'broken line'.
The RS232C port of your PC uses voltages rather than currents to indicate
logical states: 'space' is signaled by +3v to +15v (typically +12v), 'mark'
by -3v to -15v (typically -12V). The typical output impedance of the serial
port of a PC is 2 kiloohms (resulting in about 5ma @ 10v), the typical input
impedance is about 4.3 kiloohms, so there should be a maximum fan-out of 5
(5 inputs can be connected to 1 output). Please don't rely on this, it may
differ from PC to PC.
Three lines (RX, TX & ground) are needed.
Q. Why does my PC have a 25pin/9pin connector if there are only 3 lines
needed?
A. There are several status lines that are only used with a modem. See the
software section of this FAQ.
Q. How can I easily connect two PCs by a three-wire lead?
A. This connection is called a 'null-modem' connection. RX1 is connected
to TX2 and vice versa, GND1 to GND2. In addition to this, connect RTS
to CTS & DCD and DTR to DSR (modem software often relies on that). See
the hardware section for further details.
Hardware
========
The connectors
--------------
PCs have 9pin/25pin male SUB-D connectors. The pin layout is as follows
(looking at the back side of your PC):
1 13 1 5
_______________________________ _______________
\ . . . . . . . . . . . . . / \ . . . . . /
\ . . . . . . . . . . . . / \ . . . . /
--------------------------- -----------
14 25 6 9
Name (V24) 25pin 9pin Dir Full name Remarks
--------------------------------------------------------------------------
TxD 2 2 o Transmit Data
RxD 3 3 i Receive Data
RTS 4 5 o Request To Send
CTS 5 8 i Clear To Send
DTR 20 4 o Data Terminal Ready
DSR 6 6 i Data Set Ready
RI 22 9 i Ring Indicator
DCD 8 1 i Data Carrier Detect
GND 7 5 - Signal ground
- 1 - - Protective ground Don't use this one!
SCTE 24 - - Sync. clock trans. end Several PCs only
SCT 15 - o Sync. clock TX dito.
SCR 17 - i Sync. clock RX dito.
The most important lines are RxD, TxD, and GND. Others are used with
modems, printers and plotters to indicate internal states or to use
synchroneous transmission (this is rarely used, and most PCs don't support
it).
'0' means +3v to +15V, '1' means -3v to -15v. '1' is the active state.
The lines are:
RxD, TxD: These lines carry the data.
RTS, CTS: Are used by the PC and the modem/printer/whatsoever (further
on referred to as the data set) to start/stop a communication. The PC
sets RTS to its active state ('1'), and the data set responds with CTS
'1' (always in this order). If the data set wants to stop/interrupt the
communication (e.g. buffer overflow), it drops CTS to '0'; the PC uses
RTS to control the data flow.
DTR, DSR: Are used to establish a connection at the very beginning, i.e.
the PC and the data set 'shake hands' first to assure they are both
present. The PC sets DTR to '1', and the data set answers with DSR
'1'. Modems often indicate hang-up by resetting DSR to '0'.
(These six lines plus GND are often referred to as '7 wire'-connection or
'hand shake'-connection.)
DCD: The modem uses this line to indicate that it has detected the
carrier of the modem on the other side of the line.
RI: The modem uses this line to signal that 'the phone rings' (even if
there isn't a bell fitted to your modem).
SCTE, SCT, SCR: forget about these.
Protective ground: This line is connected to the power ground of the
serial adapter. It should not be used as a signal ground, and it
MUST NOT be connected to GND (even if your DMM shows up a
connection!). Connect this line to the screen of the lead (if there is
one).
Technical data (typical):
Signal level: -10.5v/+11v
Short circuit current: 6.8ma (yes, that's enough for your mouse!)
Output impedance: 2 kiloohms
Input impedance: 4.3 kiloohms
Connecting devices
------------------
Normally, a 7 wire connection is used. Connect:
GND1 to GND2
RxD1 to TxD2
TxD1 to RxD2
DTR1 to DSR2
DSR1 to DTR2
RTS1 to CTS2
CTS1 to RTS2
If a modem is connected, add lines for the following:
RI, DCD
If software wants it, connect DCD1 to CTS1 and DCD2 to CTS2.
BEWARE! While PCs use pin 2 for RxD and pin 3 for TxD, modems normally
have those pins reversed! This allows to easily connect pin1 to pin1, pin2
to pin 2 etc. If you connect two PCs, cross RxD and TxD.
If hardware handshaking is not needed, a so-called null-modem connection
can be used. Connect:
GND1 to GND2
RxD1 to TxD2
TxD1 to RxD2
Additionally, connect (if software needs it):
RTS1 to CTS1 & DCD1
RTS2 to CTS2 & DCD2
DTR1 to DSR1
DTR2 to DSR2
You won't need long wires for these!
The null-modem connection is used to establish an XON/XOFF-transmission
between two PCs (see software section for details).
Remember: the names DTR, DSR, CTS & RTS refer to the lines as seen from
the PC. This means that for your data set DTR & RTS are incoming signals
and DSR & CTS are outputs!
Base addresses & interrupts
---------------------------
Normally, the following list is correct:
Port Base address Int #
COM1 0x3F8 0xC
COM2 0x2F8 0xB
COM3 0x3E8 0xC
COM4 0x2E8 0xB
In PCs, serial communication is realized with a set of three chips
(there are no further components needed!): a UART (Universal Asynchroneous
Receiver/Transmitter) and two line drivers. Normally, the 82450/16450/8250
does the 'brain work' while the 1488 and 1489 drive the lines.
The chips are produced by many manufacturers; it's of no importance
which letters are printed in front of the numbers (mostly NS for National
Semiconductor). Don't regard the letters behind the number also; they just
indicate special features and packaging (Advanced, FIFO, New, MILitary,
bug fixes [see below] etc.).
You might have heard of the possibility to replace the 16450 by a 16550A
to improve reliability and software throughput. This is only useful if your
software is able to use the FIFO (first in-first out) buffer features. The
chips are fully pin-compatible except for two pins that are not used by
any board known to the author: pin 24 (CSOUT, chip select out) and pin 29
(NC, no connection to be made). With the 16550A, pin 24 is -TXRDY and pin
29 is -RXRDY, signals that aren't needed and that even won't care if they
are shorted to +5v or ground. Therefore it should always be possible to
simply replace the 16450 by the 16550A - even if it's not always useful due
to lacking software capabilities. IT IS DEFINITELY NOT NECESSARY FOR
COMMUNICATION UP TO LOUSY 9600 BAUD! These rates can easily be handled by
any CPU and the interrupt-driven communication won't slow down the computer
substantially. But if you want to use high-speed transfer with or without
using the interrupt features (i.e. by 'polling'), it is recommended to use
the 16550A in order to make transmission more reliable if your software
supports it (see excursion some pages below).
How to detect which chip is used
--------------------------------
This is really not difficult. The 8250 has no scratch register (see data
sheet info below), the 16450/82450 has no FIFO, the 16550 has no working
FIFO :-) and the 16550A performs alright. See the software section for
an example.
Data sheet information
----------------------
Some hardware information taken from the data sheet of National
Semiconductor (shortened and commented):
Pin description of the 16450(16550A) [Dual-In-Line package]:
+-----+ +-----+
D0 -| 1 +-+ 40|- VCC
D1 -| 2 39|- -RI
D2 -| 3 38|- -DCD
D3 -| 4 37|- -DSR
D4 -| 5 36|- -CTS
D5 -| 6 35|- MR
D6 -| 7 34|- -OUT1
D7 -| 8 33|- -DTR
RCLK -| 9 32|- -RTS
SIN -| 10 31|- -OUT2
SOUT -| 11 30|- INTR
CS0 -| 12 29|- NC (-RXRDY)
CS1 -| 13 28|- A0
-CS2 -| 14 27|- A1
-BAUDOUT -| 15 26|- A2
XIN -| 16 25|- -ADS
XOUT -| 17 24|- CSOUT (-TXRDY)
-WR -| 18 23|- DDIS
WR -| 19 22|- RD
VSS -| 20 21|- -RD
+-------------+
A0, A1, A2, Register Select, Pins 26-28:
Address signals connected to these 3 inputs select a UART register for
the CPU to read from or to write to during data transfer. A table of
registers and their addresses is shown below. Note that the state of the
Divisor Latch Access Bit (DLAB), which is the most significant bit of the
Line Control Register, affects the selection of certain UART registers.
The DLAB must be set high by the system software to access the Baud
Generator Divisor Latches.
DLAB A2 A1 A0 Register
0 0 0 0 Receive Buffer (read) Transmitter Holding Reg. (write)
0 0 0 1 Interrupt Enable
x 0 1 0 Interrupt Identification (read)
x 0 1 0 FIFO Control (write) (undefined on the 16450. CB)
x 0 1 1 Line Control
x 1 0 0 Modem Control
x 1 0 1 Line Status
x 1 1 0 Modem Status
x 1 1 1 Scratch (special use on some boards. CB)
1 0 0 0 Divisor Latch (LSB)
1 0 0 1 Divisor Latch (MSB)
-ADS, Address Strobe, Pin 25: The positive edge of an active Address
Strobe (-ADS) signal latches the Register Select (A0, A1, A2) and Chip
Select (CS0, CS1, -CS2) signals.
Note: An active -ADS input is required when Register Select and Chip
Select signals are not stable for the duration of a read or write
operation. If not required, tie the -ADS input permanently low. (As it is
done in your PC. CB)
-BAUDOUT, Baud Out, Pin 15: This is the 16 x clock signal from the
transmitter section of the UART. The clock rate is equal to the main
reference oscillator frequency divided by the specified divisor in the
Baud Generator Divisor Latches. The -BAUDOUT may also be used for the
receiver section by tying this output to the RCLK input of the chip. (Yep,
that's true for your PC. CB).
CS0, CS1, -CS2, Chip Select, Pins 12-14: When CS0 and CS1 are high and CS2
is low, the chip is selected. This enables communication between the UART
and the CPU.
-CTS, Clear To Send, Pin 36: When low, this indicates that the modem or
data set is ready to exchange data. This signal can be tested by reading
bit 4 of the MSR. Bit 4 is the complement of this signal, and Bit 0 is '1'
if -CTS has changed state since the previous reading (bit0=1 generates an
interrupt if the modem status interrupt has been enabled).
D0-D7, Data Bus, Pins 1-8: Connected to the data bus of the CPU.
-DCD, Data Carrier Detect, Pin 38: blah blah blah, can be tested by
reading bit 7 / bit 3 of the MSR. Same text as -CTS.
DDIS, Driver Disable, Pin 23: This goes low whenever the CPU is reading
data from the UART.
-DSR, Data Set Ready, Pin 37: blah, blah, blah, bit 5 / bit 1 of MSR.
-DTR, Data Terminal Ready, Pin 33: can be set active low by programming
bit 0 of the MCR '1'. Loop mode operation holds this signal in its
inactive state.
INTR, Interrupt, Pin 30: goes high when an interrupt is requested by the
UART. Reset low by the MR.
MR, Master Reset, Pin 35: Schmitt Trigger input, resets internal registers
to their initial values (see below).
-OUT1, Out 1, Pin 34: user-designated output, can be set low by
programming bit 2 of the MCR '1' and vice versa. Loop mode operation holds
this signal inactive high.
-OUT2, Out 2, Pin 31: blah blah blah, bit 3. (Used in your PC to connect
the UART to the interrupt line of the slot when '1'. CB)
RCLK, Receiver Clock, Pin 9: This input is the 16 x baud rate clock for
the receiver section of the chip. (Normally connected to -BAUDOUT, as in
your PC. CB)
RD, -RD, Read, Pins 22 and 21: When Rd is high *or* -RD is low while the
chip is selected, the CPU can read data from the UART. (One of these is
normally tied. CB)
-RI, Ring Indicator, Pin 39: blah blah blah, Bit 6 / Bit 2 of the MSR.
(Bit 2 indicates only change from active low to inactive high! Curious,
isn't it? CB)
-RTS, Request To Send, Pin 32: blah blah blah, see DTR (Bit 1).
SIN, Serial Input, Pin 10.
SOUT, Serial Output, Pin 11: ... Set to 'space' (high) upon MR.
-RXRDY, -TYRDY: refer to NS data sheet. Those pins are used for DMA
channeling. Since they are not connected in your PC, I won't describe them
here.
VCC, Pin 40, +5v
VSS, Pin 20, GND
WR, -WR: same as Rd, -RD for writing data.
XIN, XOUT, Pins 16 and 17: Connect a crystal here (1.5k betw. xtal & pin 17)
and pin 16 with a capacitor of approx. 20p to GND and other xtal conn. 40p
to GND. Resistor of approx. 1meg parallel to xtal. Or use pin 16 as an input
and pin 17 as an output for an external clock signal.
Absolute Maximum Ratings:
Temperature under bias: 0 C to +70 C
Storage Temperature: -65 C to 150 C
All input or output voltages with respect to VSS: -0.5v to +7.0v
Power dissipation: 1W
Further electrical characteristics see the very good data sheet of NS.
UART Reset Configuration
Register/Signal Reset Control Reset State
--------------------------------------------------------------------
IER MR 0000 0000
IIR MR 0000 0001
FCR MR 0000 0000
LCR MR 0000 0000
MCR MR 0000 0000
LSR MR 0110 0000
MSR MR xxxx 0000 (according to signals)
SOUT MR high
INTR (RCVR errs) Read LSR/MR low
INTR (data ready) Read RBR/MR low
INTR (THRE) Rd IIR/Wr THR/MR low
INTR (modem status) Read MSR/MR low
-OUT2 MR high
-RTS MR high
-DTR MR high
-OUt1 MR high
RCVR FIFO MR/FCR1&FCR0/DFCR0 all bits low
XMIT FIFO MR/FCR1&FCR0/DFCR0 all bits low
Known problems with several chips
---------------------------------
(From material Madis Kaal received from Dan Norstedt)
8250 and 8250-B:
* These UARTs pulse the INT line after each interrupt cause has
been serviced (which none of the others do). [Generates interrupt
overhead. CB]
* The start bit is about 1 us longer than it ought to be. [This
shouldn't be a problem. CB]
* 5 data bits and 1.5 stop bits doesn't work.
* When a 1 bit is written to the bit 1 (Tx int enab) in the IER,
a Tx interrupt is generated. This is an erroneous interrupt
if the THRE bit is not set. [So don't set this bit as long as
the THRE bit isn't set. CB]
* The first valid Tx interrupt after the Tx interrupt is enabled
is probably missed. Suggested workaround:
1) Wait for the TRHE bit to become set.
2) Disable CPU interrupts.
3) Write Tx interrupt enable to the IER.
4) Write Tx interrupt enable to the IER, again.
5) Enable CPU interrupts.
* The TSRE (bit 6) doesn't work properly.
* If both the Rx and Tx interrupts are enabled, and a Rx interrupt
occurs, the IIR indication may be lost; Suggested workarounds:
1) Test THRE bit in the Rx routine, and either set IER bit 1
or call the Tx routine directly if it is set.
2) Test the THRE bit instead of using the IIR.
* [If one of these chips vegetates in your PC, go get your solder
iron heated... CB]
8250A, 82C50A, 16450 and 16C450:
* (Same problem as above:)
If both the Rx and Tx interrupts are enabled, and a Rx interrupt
occurs, the IIR indication may be lost; Suggested workarounds:
1) Test THRE bit in the Rx routine, and either set IER bit 1
or call the Tx routine directly if it is set.
2) Test the THRE bit instead of using the IIR.
3) [Don't enable both interrupts at the same time. I've never
had any need to do this. CB]
16550 (without the A):
* Rx FIFO bug: Sometimes a FIFO will get extra characters.
[This seemed to be very embarracing for NS; they've added a
simple detection method in the 16550A (bit 6 of IIR). CB]
No bugs reported in the 16550A (yet?)
[Same is true for the 16C552, a two-in-one version of the 16550A. CB]
Software
========
First some information from the data sheet. Then: HOW TO USE IT.
Register Description
--------------------
See "Hardware" for addresses.
Register Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
RBR (r/o) ----------------------- data bits received ------------------------
THR (w/o) ------------------ data bits to be transmitted --------------------
IER ERBFI ETBEI ELSI EDSSI 0 0 0 0
IIR (r/o) pending IID0 IID1 IID2 0 0 FIFO en FIFOen
FCR (w/o) enable RFres XFres DMAsel 0 0 - RX trigger -
LCR - word length - stopbits PAR en even sel stick par SBR DLAB
MCR DTR RTS OUT1 OUT2 Loop 0 0 0
LSR RBF OE PE FE Break THRE TEMT FIFOerr
MSR DCTS DDSR TERI DDCD CTS DSR RI DCD
ERBFI: Enable Receiver Buffer Full Interrupt
ETBEI: Enable Transmitter Buffer Empty Interrupt
ELSI: Enable Line Status Interrupt
EDSSI: Enable Delta Status Signals Interrupt
IID#: Interrupt IDentification
RFres: Receiver FIFO reset
XFres: Transmitter FIFO reset
SBR: Set BReak
RBF: Receiver Buffer Full (Data Available)
OE: Overrun Error
PE: Parity Error
FE: Framing Error
THRE: Transmitter Holding Register Empty (new data can be written to THR)
TEMT: Transmitter Empty (last word has been sent)
DCTS: Delta Clear To Send
DDSR: Delta Data Set Ready
TERI: Trailing Edge Ring Indicator
DDCD: Delta Data Carrier Detect
LCR (Line Control Register):
Bit 1 Bit 0 word length Bit 2 Stop bits
0 0 5 bits 0 1
0 1 6 bits 1 1.5/2
1 0 7 bits (1.5 if word length is 5)
1 1 8 bits (1.5 does not work with some chips, see above)
Bit 5 Bit 4 Bit 3 Parity type Bit 6 SOUT condition
x x 0 no parity 0 normal operation
0 0 1 odd parity 1 force 'mark' (break)
0 1 1 even parity Bit 7 DLAB
1 0 1 mark parity 0 normal registers
1 1 1 space parity 1 divisor at reg 0, 1
Baud Rate Generator:
DLAB must be set. Write word (16 bits) to address 0 of the UART (this is
the base address) to program baud rate as follows:
xtal frequency in Hz / 16 / rate = divisor
Your PC uses an xtal frequency of 1.8432 MHz.
Do *NOT* use 0 as a divisor (your maths teacher told you so)! [It
results in a rate of some 1000 baud. CB]
An error of up to 5 percent is irrelevant.
Some values:
Baud rate Divisor (hex) Percent Error
50 900 0.0%
75 600 0.0%
110 417 0.026%
134.5 359 0.058%
150 300 0.0%
300 180 0.0%
600 C0 0.0%
1200 60 0.0%
1800 40 0.0%
2000 3A 0.69%
2400 30 0.0%
3600 20 0.0%
4800 18 0.0%
7200 10 0.0%
9600 C 0.0%
19200 6 0.0%
38400 3 0.0%
56000 2 2.86%
115200 1 0.0%
NS specifies that the 16550A is capable of 256 kbaud if you use a 4 MHz
or an 8 MHz crystal. But a staff member of NS Germany (I know that this
abbreviation is not well-chosen :-( ) told one of my friends on the phone
that it runs correctly at 512 kbaud as well, but I don't know if the
1488/1489 manage this. This is true for the 16C552, too.
BTW: Ever tried 1.76 baud? Kindergarten kids write faster.
Mice typically use 2400 baud, 8n1.
LSR (Line Status Register):
Bit 0 Data Ready (DR). Reset by reading RBR.
Bit 1 Overrun Error (OE). Reset by reading LSR. Indicates loss of data.
Bit 2 Parity Error (PE). Indicates transmission error. Reset by LSR.
Bit 3 Framing Error (FE). Indicates missing stop bit. Reset by LSR.
Bit 4 Break Indicator (BI). Set if 'space' for more than 1 word. Reset
by LSR.
Bit 5 Transmitter Holding Register Empty (THRE). Indicates that a new
word can be written to THR. Reset by writing THR.
Bit 6 Transmitter Empty (TEMT). Indicates that no transmission is
running. Reset by reading LSR.
Bit 7 Set if at least 1 word in FIFO has been received with an error.
Cleared by reading LSR if there is no further error in the FIFO.
FCR (FIFO Control Register):
Bit 0: FIFO enable.
Bit 1: Clear receiver FIFO. This bit is self-clearing.
Bit 2: Clear transmitter FIFO. This bit is self-clearing.
Bit 3: DMA mode (pins -RXRDY and -TXRDY), see sheet
Bits 6-7:Trigger level of the DR-interrupt.
Bit 7 Bit 6 Receiver FIFO trigger level
0 0 01
0 1 04
1 0 08
1 1 14
Excursion: why and how to use the FIFOs (by Scott C. Sadow)
-----------------------------------------------------------
Normally when transmitting or receiving, the UART generates an
interrupt for every character sent or received. For 2400 baud, typically
this is 240/second. For 115,200 baud, this means 11,520/second. With FIFOs
enabled, the number of interrupts is greatly reduced. For transmit
interrupts, the UART indicates the transmit holding register is not busy
until the 16 byte FIFO is full. A transmit hold register empty interrupt
is not generated until the FIFO is empty (last byte is being sent) Thus,
the number of transmit interrupts is reduced by a factor of 16. For
115,200 baud, this means only 7,200 interrupts/second. For receive data
interrupts, the processing is similar to transmit interrupts. The main
difference is that the number of bytes in the FIFO before generating an
interrupt can be set. When the trigger level is reached, a recieve data
interrupt is generated, but any other data received is put in the FIFO.
The receive data interrupt is not cleared until the number of bytes in the
FIFO is below the trigger level.
To add 16550A support to existing code, there are 2 requirements.
1) When reading the IIR to determine the interrupt source, only
use the lower 3 bits.
2) After the existing UART initialization code, try to enable the
FIFOs by writing to the FCR. (A value of C7 hex will enable FIFO mode,
clear both FIFOs, and set the receive trigger level at 14 bytes) Next,
read the IIR. If Bit 6 of the IIR is not set, the UART is not a
16550A, so write 0 to the FCR to disable FIFO mode.
IIR (Interrupt Identification Register):
Bit 3 Bit 2 Bit 1 Bit 0 Priority Source Description
0 0 0 1 none
0 1 1 0 highest Status OE, PE, FE or BI of the
LSR set. Serviced by
reading the LSR.
0 1 0 0 second Receiver DR or trigger level rea-
ched. Serviced by read-
ing RBR 'til under level
1 1 0 0 second FIFO No Receiver FIFO action
since 4 words' time
(neither in nor out) but
data in RX-FIFO. Serviced
by reading RBR.
0 0 1 0 third Transm. THRE. Serviced by read-
ing IIR (if source of
int only!!) or writing
to THR.
0 0 0 0 fourth Modem One of the delta flags
in the MSR set. Serviced
by reading MSR.
Bit 6 & 7: 16550A: set if FCR bit 0 set.
16550: bit 7 set, bit 6 cleared
others: clear
In most software applications bits 3, 6 & 7 should be masked when servicing
the interrupt since they are not relevant. These bits cause trouble with
old software relying on that they are cleared...
NOTE! Even if some of these interrupts are masked, the service routine
can be confronted with *all* states shown above when the IIR is loop-polled
until bit 0 is set. Check examples.
IER (Interrupt Enable Register):
Bit 0: If set, DR interrupt is enabled.
Bit 1: If set, THRE interrupt is enabled.
Bit 2: If set, Status interrupt is enabled.
Bit 3: If set, Modem status interrupt is enabled.
MCR (Modem Control Register):
Bit 0: Programs -DTR. If set, -DTR is low and the DTR pin of the port is
'1'.
Bit 1: Programs -RTS.
Bit 2: Programs -OUT1. Not used in a PC.
Bit 3: Programs -OUT2. If set, interrupts generated by the UART are trans-
ferred to the ICU (Interrupt Control Unit).
Bit 4: '1': local loopback. All outputs disabled.
MSR (Modem Status Register):
Bit 0: Delta CTS. Set if CTS has changed state since last reading.
Bit 1: Delta DSR. Set if DSR has changed state since last reading.
Bit 2: TERI. Set if -RI has changed from low to high (i.e. RI at port
has changed from '1' to '0').
Bit 3: Delta DCD. Set if DCD has changed state since last reading.
Bit 4: CTS. 1 if '1' at port.
Bit 5: DSR.
Bit 6: RI. If loopback is selected, it is equivalent to OUT1.
Bit 7: DCD.
--
---------------------------------------------------------------------
Christian Blum Universitaet des Saarlandes, Germany
Friedrich-Ebert-Str. 50 chbl@stud.uni-sb.de
W-6685 Heiligenwald chbl@sbustd.rz.uni-sb.de
Germany Tel (+49) (0) 6821 67476
Technical Details
Message-ID:
<1k0du6INNgkv@coli-gate.coli.uni-sb.de>Path:
arc1-ca.pugleaf.net!sparky!uunet!cs.utexas.edu!qt.cs.utexas.edu!yale.edu!ira.uka.de!sbusol.rz.uni-sb.de!coli.uni-sb.de!sbustd!chblShow Full Headers
Complete Article Headers
Path: arc1-ca.pugleaf.net!sparky!uunet!cs.utexas.edu!qt.cs.utexas.edu!yale.edu!ira.uka.de!sbusol.rz.uni-sb.de!coli.uni-sb.de!sbustd!chbl From: chbl@sbustd.rz.uni-sb.de (Christian Blum) Newsgroups: comp.sys.ibm.pc,comp.sys.ibm.pc.programmer,comp.sys.ibm.pc.hardware Subject: FAQ serial port (part one) Date: 25 Jan 1993 10:03:50 GMT Organization: Studenten-Mail, Rechenzentrum Universitaet des Saarlandes Lines: 757 Message-ID: <1k0du6INNgkv@coli-gate.coli.uni-sb.de> NNTP-Posting-Host: sbustd.stud.uni-sb.de