🚀 go-pugleaf

In article <4781@aplcen.apl.jhu.edu> gotwols@warper.jhuapl.edu (Bruce Gotwols) writes:
>I recently acquired an analog to digital (A/D) board which uses DMA to transfer
>the digitized data to an IBM AT.  In a short note in the instruction manual
>it warned that data may be sporadically lost on machines with either EGA or VGA
>screens if the user writes to the screen while DMA is in progress.  The claim is
>that the act of writing to the screen (on EGA and CGA only) involves using the
>processors Non Maskable Interrupt (NMI), and since the NMI has higher
>priority than DMA it may keep things tied up long enough that the next A/D
>sample comes in before the last one is safely stored in memory.
>

Writing to the EGA and VGA screens definitely does not involve NMI.  What
the A/D board maker probably meant that the CRT controller in an EGA uses two
(2) out of five (5) memory cycles for screen refresh in low resolution
modes and 4/5 memory cycles in high resolution modes.  That is screen
memory of course.  So when user program writes to screen buffer, it gets
only 1 out of 5 or 3 out of 5 memory cycles.  I'm no H/W expert so I don't
really understand how that would affect the A/D board's DMA capability.
Anyone care to comment on that?

With CGA and MDA cards it is possible to generate an NMI by writing to the
6845 MODE register, so that CRTC will be reprogrammed by the interrupt
service routine.  Weird, isn't it?

-- 

Jyrki Tuomi
Internet:  jt19840@tut.fi    UUCP:  ..mcvax!tut!jt19840