Article View: comp.sys.ibm.pc
Article #43560Re: Memory cache *and* zero wait state?
From: Brent Besler
Date: Mon, 19 Feb 1990 18:49
Date: Mon, 19 Feb 1990 18:49
8 lines
1034 bytes
1034 bytes
I have seen 60 ns 1 Mbit DRAM chips and SIMM/SIPP's made from them at a few mail order placesd in the last month. The fastest SRAM chips I have seen are 25 ns, but read in Byte that Toshiba is developing 15 ns ones. I doubt SRAM will ever replace DRAM in micros. It is too expensive. In the fastest mainframes, the memory is all SRAM. On the Cray-XMP, they have to use special interleaving procedures to get the ram to keep up with the CPU even with its very fast memory. The Cray uses ECL(emmiter coupled logic) RAM, I believe, which is probably close to 10 ns.
Technical Details
Message-ID:
<139@vela.acs.oakland.edu>Path:
arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!usc!samsung!umich!vela!bbeslerReferences:
<25dc04c8@ralf> <1860@clyde.concordia.ca>Show Full Headers
Complete Article Headers
Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!usc!samsung!umich!vela!bbesler From: bbesler@vela.acs.oakland.edu (Brent Besler) Newsgroups: comp.sys.ibm.pc Subject: Re: Memory cache *and* zero wait state? Message-ID: <139@vela.acs.oakland.edu> Date: 19 Feb 90 18:49:47 GMT References: <25dc04c8@ralf> <1860@clyde.concordia.ca> Reply-To: bbesler@vela.acs.oakland.edu (Brent Besler) Organization: Oakland University, Rochester MI Lines: 8