🚀 go-pugleaf

In article 8757@ccu1.aukuni.ac.nz, stuartw@ccu1.aukuni.ac.nz (Stuart Woolford) writes:
>mash@mash.wpd.sgi.com (John R. Mashey) writes:
>
>I have heard ( I think it was in a BYTE article, and from other people.. ) that
>the P5 has run one of the major FP Benchmarks ( Wheatstone, Linpack, I cannot remember ) at 66MFlops for a 66MHz clock speed, if this is even close to true,
>then I think it will be a contender, and these 'facts' were attributed to a
>report from Intel's Hardware people, NOT Salesmen. They also stated that the
>maximum cycles for a FP Instruction was 3 cycles, and there were 2 Integer
>Pipelines....
>
>and remember    !!!!These are not facts, just what I have heard!!!!

Hmmm... yet the same world-of-rumour tells tales of P5's to date clocking at a
maximum of 40Mhz (30Mhz with FP enabled).... I wonder what 66Mhz P5 part this is B)

Of course it could just have been an extrapolation from current chip cuts....

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