Cache controllers

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Article #102

#102

From: Tim McCaffrey
Date: Thu, 23 Jul 1992 21:55

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 Does anyone have a list of cache controllers that work with the
 486 and what their charteristics are? (background write back,
 n-way set associative, number of wait states on cache miss,
 bus snooping, etc).  Also, does anybody have any statistics
 for the hit ratios of a large (> 1Meg) 16 bit protected mode
 application with various cache sizes and types? 

 We have the Intel databook, but that doesn't tell much how the
 data was arrived at (probably DOS real mode apps :( ).

		     ADthanksVANCE

				Tim McCaffrey

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Path: arc1-ca.pugleaf.net!sparky!uunet!paladin.american.edu!darwin.sura.net!udel!gvls1!tredysvr!asns!tmm
From: tmm@dvnspc1.Dev.Unisys.COM (Tim McCaffrey)
Newsgroups: comp.sys.intel
Subject: Cache controllers
Message-ID: <1992Jul23.215528.8807@dvnspc1.Dev.Unisys.COM>
Date: 23 Jul 92 21:55:28 GMT
Organization: Unisys - Tredyffrin Engineering Offices
Lines: 14