🚀 go-pugleaf

In article <veit.664529461@du9ds3> veit@du9ds3.uni-duisburg.de (Holger Veit) writes:
>dix@clinet.fi (Risto Kaivola) writes:
>
>>more precise, I need information on the 'internal representation' of
>>the instruction set. This term isn't probably the right one to use in
>>Intel world, so I'll provide an example. Given that there is an operand
>>'move', which copies the contents of a register to another, and we have
>>the following instruction in an assembly language program:
>> 
>>    move register1, register2
>
>>The 'internal representation' of this instruction might be 0x56750102.
>>That is, 'internal representation' is 'what the instruction looks in
>>memory'.
i had the same problem when i started my project; i guess that you are
asking for material which is under properitaryship of INTEL; no way you
can find out; in the past however i got in touch with this guy at INTEL
thro' someone, and he was willing to answer only the specifics; if i asked
him A he would answer yes/no. period; in the mean time i did a lot of
brain storming with comp.arch, research was done with BYTE magazine,
microprocessor report; perhaps your best bet is to get in touch with mike
slater (of the microprocessor report) and ask him; he gets privy to all
these materials; 
good luck; also try to read between lines in manuals; it helps; i found
that my implementation of the predecode unit was right after figuring out
a logical implemantation; turns out that there is a specific terminology
assoc. with that; also i realized that my implementation would work faster
based on states (or some thing similar) if i could avoid the queue after
reset; this is called cache bypass i found out later;
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Bharat P. Savel
EE Dept.                                       E-mail : savel@hoss.unl.edu
Univ of Nebraska-Lincoln                           Ph : (402) 477-9857