🚀 go-pugleaf

I'm currently modifying a peice of time critical assembler code for a rather
old 8088 based system and I'd like to be able to work out *exactly* how long
my new code will take to execute.

From reading Intel's iAPX86,88 User Manual I can get figures for the no. of
_clocks_ for each instruction but how do _clocks_ relate to bus cycles. From
what I've read it would appear that each bus cycle is broken into at least
four clock cycles (T1 - T4) + wait states + idle cycles.

The heart of the code I'm planning to introduce will include a REP MOVSW to
copy a 64 byte string as 32 words. The code is held in EPROM (running with 2
wait states) the source and destination strings are both in RAM (with one
wait state). The timings for REP MOVSW are quoted as 9 + 17/rep (8086) and 9
+ 21/rep for an 8088.

Given that the 8088 is running at 5MHz then with no wait states the transfer
of 32 words would take 9 + 21*32 = 681 clocks = 136.2uS

REP MOVSB is coded as two bytes and therefore I'd guess that the 2 wait
states on the EPROM would add 4 clocks to the overall time. But do the wait
states on the RAM also add a further 2 clocks (1 read/1 write) per byte
transfered?

I'd be very grateful if someone could let me know how the wait states will
affect the timing.

	Dave
Dave Lumby, Software Maintene[e]ance Group, Software Technology Division, BT
Research Labs, Martlesham Heath, Ipswich, IP5 7RE, UK
Phone:  +44 473 642613
E-mail: dlumby@axion.bt.co.uk
"I don't mind valid criticism, as long as it doesn't come from other people"