🚀 go-pugleaf

A number of people in various newsgroups have requested information concerning
the performance of the i860 and/or i860 compilers.  A study just completed
at the University of Virginia examines in depth the processor-memory
interrelationship for a board consisting of an i860 and memory subsystem
constructed from page-mode DRAMs.

From an understanding of this interrelationship, guidelines are established
for implementing inner-loop operations in a manner consistent with the
processor architecture and memory system performance characteristics; by
adhering to these guidelines the assembly language programmer or compiler
writter can realize a 200-300% increase in performance over code generated
in a "straight-forward" fashion.

The implementation techniques presented throughout the report are dependent
on a memory system constructed with static-column or page-mode DRAMs. In
addition, the report focuses on vector operations (BLAS-like routines) and
scientific computations built on top of them.

To receive a copy of this report, send a request to:

                                 Brenda Lynch
                      Institute for Parallel Computation
                  School of Engineering and Applied Science
                             University of Virginia
                          Charlottesville, VA   22903


                     or   bhl7u@virginia.edu


ask for  IPC-TR-91-007 "Performance of the iPSC/860 Node Architecture"


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| Steve Moyer                    |       THIS SPACE FOR RENT         |
| University of Virginia         |                                   |
|                                | "Just a rebel without a clue..."  |
| E-mail: sam2y@virginia.edu     |                - The Replacements |
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