🚀 go-pugleaf

I've been following the discussion on the different x86 processors
with some interest as I have a Sun386i with a 20 MHz 38{6,7}DX pair.
I've been thinking of replacing the 386 with a Cyrix 486DLC, which
would be a pop-in. My concern is how is cache coherency handled in
this (or these kind of) processor? I assume that the cache can be set
up only to cache RAM, but what about DMA transfers? Is the cache
controller part listening to DMA requests or does it flush the cache
on bus requests? 

I'm not all that familiar with the intel junk, I've mostly been
working with Motorola 68k family processors.

I'm also interested in how to set up the 486DLC cache.

Note that this machine runs SunOS, not messy dos or windoze.

Thanks,
Thomas
--
Real life:      Thomas Tvrnblom           Email:  Thomas.Tornblom@Nexus.Comm.SE
Snail mail:     Communicator Nexus AB     Phone:  +46 18 171814
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                S - 751 08 Uppsala, Sweden