Re: 486/66 .. Into a 486/50 motherboard?

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Article #1138

#1138

From: John F Carr
Date: Thu, 24 Dec 1992 01:04

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In article <BzFnyr.IHI@wimsey.bc.ca> sl@wimsey.bc.ca (Stuart Lynne) writes:
>Since 20 nanosecond SRAM still needs wait states to run with 33 Mhz clock I 
>suspect it will be a while before DRAM gets fast enough to run with no 
>wait states at 50 Mhz :-)

I had assumed that the 20 ns caches advertised with 486 systems were 0
wait state.  Is this not true?  How many bus cycles does it take for a
(33, 50) Mhz 486 to read (a word, a cache line) from a 20 ns secondary
cache?

--
    John Carr (jfc@athena.mit.edu)

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Message-ID: <1992Dec24.010425.19979@athena.mit.edu>

Path: arc1-ca.pugleaf.net!sparky!uunet!think.com!enterpoop.mit.edu!bloom-picayune.mit.edu!athena.mit.edu!jfc

References: <92351.46019.J056600@LMSC5.IS.LMSC.LOCKHEED.COM> <BzFnyr.IHI@wimsey.bc.ca>

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Newsgroups: comp.sys.intel
Path: arc1-ca.pugleaf.net!sparky!uunet!think.com!enterpoop.mit.edu!bloom-picayune.mit.edu!athena.mit.edu!jfc
From: jfc@athena.mit.edu (John F Carr)
Subject: Re: 486/66 .. Into a 486/50 motherboard?
Message-ID: <1992Dec24.010425.19979@athena.mit.edu>
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Organization: Massachusetts Institute of Technology
References: <92351.46019.J056600@LMSC5.IS.LMSC.LOCKHEED.COM> <BzFnyr.IHI@wimsey.bc.ca>
Date: Thu, 24 Dec 1992 01:04:25 GMT
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