🚀 go-pugleaf

In article <BzFnyr.IHI@wimsey.bc.ca> sl@wimsey.bc.ca (Stuart Lynne) writes:
>
>With a properly designed board there will be no difference in bandwidth due
>to changing between 33 & 50 Mhz. This assumes that the board is designed to 
>accomodate both speeds and the BIOS knows how to setup the RAM access wait
>states properly for the oscillator speed and RAM speed.

Actually... no.  You did point out the main memory changes, but the
VL-Bus or PCI-Bus will be running at a different rate.  In the case of
the 50, it might be at 50 or it might be a 25 (something to watch out
for).  With the 33, it will be 33.  

>Once it does this it makes no difference whether you are running 33 or 50. You
>are accessing the RAM as fast as you can. The *only* way that there would be
>a difference would be if your RAM was fast enough to run without wait states
>with a 50Mhz clock. 

DRAM or SRAM?  DRAM will run 0ws in page mode at 25MHz.  The rule of
finding out which is faster is to use (1/clock-speed) * (number of
waitstates+2+n), where the clock speed is the memory controller clock
and the number of waitstates is the number of memory waitstates and "n" is
the fudge factor (0<=n<=1).  The reason why it is the number of memory
waitstates and the reason why there is a fudge factor is that some
manufacturers operate a 50MHz DX on a 25MHz bus (which can wind up
being slower than a DX2/50).

>Since 20 nanosecond SRAM still needs wait states to run with 33 Mhz clock I 
>suspect it will be a while before DRAM gets fast enough to run with no 
>wait states at 50 Mhz :-)

It depends on the design... 20ns SRAM can access data in 20ns.  Since
the 33MHz cycle time is a minimum of 60ns, this leaves 40ns for the
address to propogate out of the cpu (~15ns), to be looked-up in the
tag (~20ns) and enough ready setup time for the 486 (~5ns)... it's tight,
but it can work.  Some less expensive caches can't handle it and do
have to use interleaving or adding of one waitstate.

>Does anyone out there know how fast memory would have to be to be used without
>wait states by a 50Mhz 486?

If you mean SRAM... 20ns is plenty fast for the data for direct mapped
caches.  But, the tags need to be about 10ns :)

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