🚀 go-pugleaf

    Well, certain tricks can also be used with multiple CPUs on the same
    die. And these have an important advantage: as far as I can see, 6
    instruction issue per cycle is virtually pointless. The *limit* of
    superscalarity present in general purpose codes is 4, and actually we
    are hard pressed to find many codes with superscalarity higher than 2.

Dave Ditzell, at Micro-25, quoted Larry Wall at ASPLOS:

"The amount of attainable parallelism is directly proportional to the
year of publication."

To which Ditzell adds (paraphrased):

<<The conference where research is being published apparently must
also be factored in to the amount of attainable parallelism. Micro
papers have more parallelism than ASPLOS papers.>>



For those who don't follow the conferences, Micro (the Conference on
Microarchitecture [with Microprogramming added in very small letters
for historical reasons]) has traditionally been the conference for new
work in superscalar, and compilers for same.  Micro was a backwater
for a while, while pipelined RISCs grabbed the spotlight, but Micro
has become much more interesting as superscalar has become standard
practice. 
--

Andy Glew, glew@ichips.intel.com
Intel Corp., M/S JF1-19, 5200 NE Elam Young Pkwy, 
Hillsboro, Oregon 97124-6497

This is a private posting; it does not indicate opinions or positions
of Intel Corp.

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