🚀 go-pugleaf

RetroBBS NetNews Server

Inspired by RockSolid Light RIP Retro Guy

Article View: comp.sys.intel
Article #1224

Re: Superscalar vs. multiple CPUs ?

#1224
From: Peter Su
Date: Thu, 17 Dec 1992 14:42
35 lines
2170 bytes
In article <PCG.92Dec13170504@aberdb.aber.ac.uk> pcg@aber.ac.uk (Piercarlo Grandi) writes:
   Precisely my point: single threaded *general purpose* codes have a
   limited intrinsic degree of exploitable parallelism .

	...

   So far the evidence seems (to me at least) that exploitable degrees of
   micro (multiple instruction issue in a cycle) and macro (multiple
   instruction streams in a program) parallelism for most codes don't go
   above 2-4; only codes with highly regular data reference patterns can be
   micro/macro parallelized with success/ease.

This sort of begs the question: if current code can't use these
architectures well because it wasn't designed to be parallel, why not
start the slow move towards code that *was* designed with these
architectures in mind?

It is possible to make irregular code (say, unstructured sparse matrix
ops) perform well, even on vector machines.  It is unlikely that a
compiler will do it for you.

It seems to me that the industry spends a huge amount of time trying
to mash old code until it runs fast when it could instead try to
figure out better algorithms and make sure that the systems needed to
get that software up fast and perform well is available.

Everyone who moves to a  new class of architectures has to expect to
rewrite their code, don't they?

Flame suit on,
Pete
--
Department of Computer Science, Duke University, Durham, NC 27706
Internet:	psu@cs.duke.edu
UUCP:		mcnc!duke!psu
Technical Details
Message-ID: <PSU.92Dec17094221@ptero.cs.duke.edu>
Path: arc1-ca.pugleaf.net!sparky!uunet!stanford.edu!rock!concert!duke!psu
References: <WAYNE.92Dec4093422@backbone.uucp> <37595@cbmvax.commodore.com> <PCG.92Dec9154602@aberdb.aber.ac.uk> <1992Dec10.002951.23336@athena.mit.edu> <PCG.92Dec13170504@aberdb.aber.ac.uk>

Show Full Headers
Complete Article Headers
Path: arc1-ca.pugleaf.net!sparky!uunet!stanford.edu!rock!concert!duke!psu
From: psu@cs.duke.edu (Peter Su)
Newsgroups: comp.sys.intel,comp.arch
Subject: Re: Superscalar vs. multiple CPUs ?
Message-ID: <PSU.92Dec17094221@ptero.cs.duke.edu>
Date: 17 Dec 92 14:42:21 GMT
References: <WAYNE.92Dec4093422@backbone.uucp> <37595@cbmvax.commodore.com>
 <PCG.92Dec9154602@aberdb.aber.ac.uk>
 <1992Dec10.002951.23336@athena.mit.edu>
 <PCG.92Dec13170504@aberdb.aber.ac.uk>
Sender: news@duke.cs.duke.edu
Followup-To: comp.sys.intel
Organization: Duke University CS Dept., Durham, NC
Lines: 35
Nntp-Posting-Host: ptero.cs.duke.edu
In-reply-to: pcg@aber.ac.uk's message of 13 Dec 92 17:05:04 GMT