Article View: comp.sys.intel
Article #1230Re: Superscalar vs. multiple CPUs ?
From: Stefan Monnier
Date: Thu, 17 Dec 1992 21:14
Date: Thu, 17 Dec 1992 21:14
28 lines
1897 bytes
1897 bytes
In article <BzAE6A.6qF@cpsc.ucalgary.ca> cleary@cpsc.ucalgary.ca (John Cleary) writes: > >So whats wrong with putting one CPU on the chip and filling the rest with >DRAM? >This might also help with the heat dissipation problem which I am told >is one of the biggest design constraints for the newer chips. >Why have lots of cool memory chips and hot CPUs, instead have lots of >luke-warm mixtures :-) >If you fill the chip with CPUs and then have to go off chip for memory >surely it is better to have the local memory close to the CPU. >You wont be able to get speedup unless each parallel CPU has a reasonably small >working set of memory anyway. >I have also wondered whether we may be reaching the point where it is better >to avoid the complexity of Superscalar etc. and just have lots of simple >CPUs with their own local memory on chip. >-- >John Cleary >University of Calgary. >cleary@cpsc.ucalgary.ca This sure has some BIG advantages (think of cache line filling: 1 (one) row access would be sufficient, with a data path between dram and cache of 256 bytes (for example)). But not for today. Don't forget the ruleofthumb: 1MIPS, 1MB, 1Mb/s. Today's processors need at least 16MB. I don't think it is possible to fit much more than a few MB on a chip, right now. But maybe in a few years, how knows ? Stefan
Technical Details
Message-ID:
<BzF9oC.G8K.2@cs.cmu.edu>Path:
arc1-ca.pugleaf.net!sparky!uunet!ogicse!das-news.harvard.edu!cantaloupe.srv.cs.cmu.edu!monnierReferences:
<1992Dec10.002348.24894@nas.nasa.gov> <BzAE6A.6qF@cpsc.ucalgary.ca>Show Full Headers
Complete Article Headers
Path: arc1-ca.pugleaf.net!sparky!uunet!ogicse!das-news.harvard.edu!cantaloupe.srv.cs.cmu.edu!monnier From: monnier+@cs.cmu.edu (Stefan Monnier) Newsgroups: comp.sys.intel,comp.arch Subject: Re: Superscalar vs. multiple CPUs ? Message-ID: <BzF9oC.G8K.2@cs.cmu.edu> Date: 17 Dec 92 21:14:34 GMT Article-I.D.: cs.BzF9oC.G8K.2 References: <1992Dec10.002348.24894@nas.nasa.gov> <BzAE6A.6qF@cpsc.ucalgary.ca> Sender: news@cs.cmu.edu (Usenet News System) Organization: School of Computer Science, Carnegie Mellon Lines: 28 Nntp-Posting-Host: j.gp.cs.cmu.edu