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Article #1290Re: Idea for the P5!
From: Jim Trethewey
Date: Thu, 19 Nov 1992 15:31
Date: Thu, 19 Nov 1992 15:31
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In article <1992Nov18.203321.18612@msuinfo.cl.msu.edu>, sundaram@eecae.msu.edu writes: > Instead of devoting part of the die to emulate 80x86 code, why not include some > instructions that will allow the P5 to act as a master processor to a true > (or slightly modified) 80x86 chip. As we have seen with other co-processor scenarios (most notably 8087, 287, and 387), you sacrifice a lot of speed by having to "go off chip" as opposed to having the functionality onboard. Although many people think the 486SX upgrade "trick" is stupid, I think it was a smart idea for exactly this performance reason. Another factor to consider is that a large percentage of the power drawn by a microprocessor is devoted to driving the I/O pins. The less you wiggle those lines, the cooler it will run. Hence another advantage of onboard cache and coprocessor functions. -- --Jim Trethewey, $WORK = flamer@mithril.intel.com, $HOME = flamer@alfirin 5200 NE Elam Young Parkway HF3-73, Hillsboro OR 97124-6497 (503)696-5444
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Newsgroups: comp.sys.intel Path: arc1-ca.pugleaf.net!sparky!uunet!zaphod.mps.ohio-state.edu!wupost!cs.utexas.edu!asuvax!chnews!hfglobe!mithril!flamer From: flamer@mithril.intel.com (Jim Trethewey @mithril) Subject: Re: Idea for the P5! Message-ID: <flamer.722187076@mithril> Sender: news@hfglobe.intel.com (News User) Nntp-Posting-Host: mithril.intel.com Organization: Intel Corporation References: <1992Nov18.203321.18612@msuinfo.cl.msu.edu> <1992Nov18.222927.20422@nas.nasa.gov> Distribution: usa Date: Thu, 19 Nov 1992 15:31:16 GMT Lines: 16