🚀 go-pugleaf

dlumby@axion.bt.co.uk (Dave Lumby) writes:


]
] I'm currently modifying a peice of time critical assembler code for a rather
] old 8088 based system and I'd like to be able to work out *exactly* how long
] my new code will take to execute.
]
] From reading Intel's iAPX86,88 User Manual I can get figures for the no. of
] _clocks_ for each instruction but how do _clocks_ relate to bus cycles. From
] what I've read it would appear that each bus cycle is broken into at least
] four clock cycles (T1 - T4) + wait states + idle cycles.
]
] The heart of the code I'm planning to introduce will include a REP MOVSW to
] copy a 64 byte string as 32 words. The code is held in EPROM (running with 2
] wait states) the source and destination strings are both in RAM (with one
] wait state). The timings for REP MOVSW are quoted as 9 + 17/rep (8086) and 9
] + 21/rep for an 8088.


In systems with prefetch queues, like the 8088, it is best to double check
with a logic analyzer. Depending on system state, execution time can be 
*slightly* indeterminate.

]
] Given that the 8088 is running at 5MHz then with no wait states the transfer
] of 32 words would take 9 + 21*32 = 681 clocks = 136.2uS
]
] REP MOVSB is coded as two bytes and therefore I'd guess that the 2 wait
] states on the EPROM would add 4 clocks to the overall time. But do the wait
] states on the RAM also add a further 2 clocks (1 read/1 write) per byte
] transfered?

The instruction fetch does not factor in to the instruction execution time.
It is assumed that the prefetch queue decouples the execution unit from ]
the bus controller.

]
] I'd be very grateful if someone could let me know how the wait states will
] affect the timing.

Wait states will add 2N (N= # of wait states per access) clocks to each
 word transferred on an 8086,
4N to each word on an 8088. This assumes that the source and destination
regions have the same wait state profile.

On the bus, it'll look like this:

T1 - T2 - TW - TW - T3 - T4 - TI - TI ....T1-T2-Tw-Tw-T4
    Fetch word	            fiddle w/word     deposit word
** This is for an 8086. An 8088 will need two fetches and two deposits
per word.

The Ti/fiddle-with-word states are necessary because the 8086/8088
is very inefficient. The 80186/80188 perform the same function
at the full bandwidth (no idle states).

--
|  Mitch Kahn              | "I hope you know that this will go down on |
|  mkahn@sedona.intel.com  |  your permanent record..."                 |
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