🚀 go-pugleaf

1] CACHE# 
The manual describes this pin as indicating the processor's
intention to cache the data on cacheable reads and code fetches.
How does the external core logic use this information? Unlike
PCD, this pin indicates the cacheability on a line-by-line
basis. Does the CACHE# pin become useful in the case where
paging is disabled, or for a cycle that is not paged? But
even in this case, the internal cacheability of the line is 
disabled since PCD=1. 

2] EWBE#
The value on this pin during reset determines the ordering
mode used. The i860XP manual mentions that in systems that do 
not have external write-buffers, this pin can be tied to Vss
for strong ordering, and to Vcc for weak ordering. This would
mean that this pin remains always asserted for strong ordering,
in systems not using external write-buffers. Is the EWBE# pin,
ignored in this case?

Any clarifications?