Article View: comp.sys.intel
Article #1647Re: 80386 Multiply: quote from Intel
From: Ken Karakotsios
Date: Fri, 21 Aug 1987 17:29
Date: Fri, 21 Aug 1987 17:29
46 lines
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2824 bytes
In article <576@obiwan.UUCP>, mark@mips.UUCP (Mark G. Johnson) writes:
>
> The July, 1987 issue of COMPUTER DESIGN magazine has an article on page 22
> "80386 Multiplier Problem Spotlights VLSI Testability Issues"
> which you might find illuminating. The following excerpt is taken
> without permission:
>
> {beginning of excerpt}
> `Contrary to industry speculation, the 80386 multiplier errors result
> from a layout problem, not from an error in logic design. "We didn't
> allow enough margin to catch the worst-case pattern in the multiplier
> at the corners of our process," explains Dana Krelle, Intel's 80386 [...]
>
> Another interesting facet of the problem hasn't been mentioned
> yet --- the 80386 doesn't have a multiplier (!!). The 386 uses
> its general-purpose ALU, plus a shift-and-add microcode routine,
> to perform multiplication operations. Similarly, divide operations
> use the ALU plus a shift-and-subtract microcode routine.
>
> The confusing thing is, why do multiplys fail but divides and
> adds (apparently) work?? Isn't it possible to supply the
> appropriate "bad" ALU operands for a regular add, or to create
> them during some step of a divide?
This is just speculation, since I know nothing about the 386 design.
If they are using a shift and add for multiplication, then they may have a
special shift-by-two-bits latch. This is useful in doing a what I think is
called a "modified Booth algorithm", where two bits worth of a multiply can
be done each clock cycle, if you can make 1x, 2x and 4x of one of the
inputs available. As far as I know, the shift by 2 bits isn't too useful
for much else. The divide algorithms I know of which don't use parallel
multipliers or groups of adders only shift by 1 bit at a time, so such a
divide wouldn't use the shift-by-two latch either. So perhaps the pattern
sensitivity lies in this shift register.
By the way, I think you can make this multiplication algorithm work for
N bits per clock cycle, if you can provide all the following multiples of one
of the inputs (call it Y) : Y, 2Y, ... (2^^N)Y .
Ken Karakotsios ken!sci
Silicon Compiler Systems
Disclaimer: These are my personal views and opinions, and don't
reflect those of my employer.
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Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: arc1-ca.pugleaf.net!utzoo!mnetor!uunet!seismo!rutgers!ames!amdahl!dlb!auspyr!sci!ken From: ken@sci.UUCP (Ken Karakotsios) Newsgroups: comp.sys.intel,comp.lsi,comp.arch Subject: Re: 80386 Multiply: quote from Intel Message-ID: <7939@sci.UUCP> Date: Fri, 21-Aug-87 13:29:29 EDT Article-I.D.: sci.7939 Posted: Fri Aug 21 13:29:29 1987 Date-Received: Thu, 27-Aug-87 01:38:14 EDT References: <576@obiwan.UUCP> Organization: Silicon Compilers Systems Corp. San Jose, Ca Lines: 46