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Article #177

Re: 486 performance

#177
From: Dennis O'Connor
Date: Tue, 04 Aug 1992 22:42
33 lines
1841 bytes
scott@unixland.natick.ma.us (Scott Evernden) writes:
] In article <> jwreilly@mipos2.UUCP (Jeffrey Reilly) writes:
] >In article <> cw1u+@andrew.cmu.edu (Chi-Tai (Frank) Wu) writes:
] >
] >On a 33MHz i486DX CPU system with 32MB of RAM and 256KB of cache:
] >
] >Dhrystone1.1 VAX MIPS: 27.6
] >Dhrystone2.1 VAX MIPS: 26.3
]
] Amazing.  When the 486/33 arrived, I remember the approx number being
] 15 mips.  Then Intel began insisting it was 21 mips.  Now I see it's
] evolved upwards again.
]
] This is encouraging.  If I just wait, my machine will eventually hit
] 100 mips and it won't cost me anything at all!

Dhrystone ratings are affected by the quality of the technology.
Intel486(tm) compiler technology has been improving (as has most other),
so it's normal to see this rise in Dhrystones even tho the chips
themselves may not have change.

According to a newspaper article, the compilers developed for "P5"
will deliver better Intel486 performance too. So you can expect
another evolution of all the numbers.

This is IMHO relatively legitamate : most applications are
in HLL, so they never really see the chip itself in any way :
they see the compiler's view of the chip.


--
Dennis O'Connor			doconnor@sedona.intel.com
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References: <MeTM3Ry00VolQH2VFv@andrew.cmu.edu> <12674@inews.intel.com> <1992Aug4.205351.3073@unixland.natick.ma.us>

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Path: arc1-ca.pugleaf.net!sparky!uunet!gatech!destroyer!sol.ctr.columbia.edu!eff!iWarp.intel.com|inews!doconnor
From: doconnor@sedona.intel.com (Dennis O'Connor)
Newsgroups: comp.sys.intel
Subject: Re: 486 performance
Message-ID: <DOCONNOR.92Aug4154227@potato.sedona.intel.com>
Date: 4 Aug 92 22:42:27 GMT
References: <MeTM3Ry00VolQH2VFv@andrew.cmu.edu> <12674@inews.intel.com>
 <1992Aug4.205351.3073@unixland.natick.ma.us>
Sender: news@inews.intel.com
Organization: Intel i960(tm) Architecture
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In-reply-to: scott@unixland.natick.ma.us's message of 4 Aug 92 20:53:51 GMT