🚀 go-pugleaf

I've run into a problem with my back-end for the MIT Scheme compiler
for the 386+387/486 architecture.

The i486 Microprocessor Programmer's Reference Manual (Osborne
McGraw-Hill's version) lists the following line in the description of
the FDIV instruction (pg. 26-87):

DC F8 + i	FDIV ST(i),ST	73	70	Replace ST(i) with ST : ST(i)

and the following line in the description of the FDIVR instruction (pg. 26-89):

DC F0 + i	FDIVR ST(i),ST	73	70	Divide ST(i) by ST

Where the columns mean

Opcode		Instruction	Clocks	Clocks*	Description

					Clocks* = Concurrent Execution.


I have reason to believe that the opcodes in these two instructions
are swapped, that is, "DC F8+i" corresponds to FDIVR and "DC F0+i"
corresponds to FDIV.

Can anyone confirm this?  

If so, is there a list of bugs in the documentation (or the hardware)
available anywhere on the net?  

Thanks.

PS: Please reply by e-mail.  I don't usually read this newsgroup.