🚀 go-pugleaf

In article <DOCONNOR.92Aug4081003@potato.sedona.intel.com>, doconnor@sedona.intel.com (Dennis O'Connor) writes:
| 
| doon@equinox.unr.edu (Harry W Reed) writes:
| ] In article <> johna@psdcae1.gvg.tek.com (John Abt) writes:
| ] >Your right - there has been so much publicity - the whole world knows what
| ] >the "P5" is.
| ]
| ] Ok then could you please enlighten us as to what exactly the P5 will be like?
| 
| (-: It will be like an Intel486(tm) on steroids and amphetamines. :-)
| (-: What more do you need to know ?                               :-)

  But the Intel handouts show a RISC processor in there, and imply large
gains in performance if you "simply recompile for maximum performance."
If the diagram in _EE Times_ (I believe) is correct, then the CISC is
there, but you are expected to use the RISC processor to get a real
performance boost.

  Is the P5 really going to be faster than the 486 (a) at the same clock
speed, and (b) running 486 code?

  I don't expect an answer, Intel suddenly tells me they "don't comment
on unannounced products," even though we have done non-disclosure with
them before, and are probably covered under another product agreement I
can't mention.

-- 
bill davidsen, GE Corp. R&D Center; Box 8; Schenectady NY 12345
    I admit that when I was in school I wrote COBOL. But I didn't compile.