🚀 go-pugleaf

This is a dumb question as I'm looking at the answer (in
the Intel manual) but I'm almost certain that I have seen
some code that contradicts it so here goes:

I am writing code to initialize protected mode and paging
on a 80386. I have two questions (and what I think the 
answers are):

1 - Does a page directory have to be aligned on a 4K boundary?
I don't think so as CR3 contains a 32 bit linear address.

2 - Does a page table have to be aligned on a 4K boundary?
I DO think so as page directory (and table) entries for the
page frame address have the low order 12 bits explicitly set
to 0. In page tables this is normal as physical memory is
split up into 4K pages so each entry can describe a page
and each different page starts on a 4K boundary. 
But for a page directory the entry is for a page table which
can be anywhere I think it should be (physically) so should I
be making sure that it does fall on a 4K boundary? The Intel
manual does not specifically say to do this but they might
not have had the ignorant in mind when they wrote it.

I am almost sure that I have things right but I have some code
(that supposedly works) that declares a structure for user
page tables in C and makes no effort to ensure that they fall
on a 4K boundary. This can't be right, can it??

Thanks,
Chuck Officer
cbo@cs.vu.nl