Re: The Jumperless Pentium Mainboard

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Article #2030

#2030

From: Peter E. Fry
Date: Mon, 18 Nov 1996 00:00

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Videoman wrote:
> Like everything else in the PC's "design", it's a bit screwed up.
> Technically, the PC could support 64 IRQs using the same PIC chip that
> it does now. The problem is, where do you put the IRQ lines on the bus
> connectors? That's a lot of pins.

  64 (or even 63) IRQs with two 8259s?  How?  And with level triggering
available, why?  Edge triggered interrupts was a cost-related decision
on the original PC, and a mistake, as it turns out.  But as far as I
know the 8259 has eight channels, period.

> The future is not hardwired IRQ lines, but a network of connected nodes
> for each device. USB is like this, and certainly more to follow.

  I imagine you may be right, there, but I'll bet PCI lasts for a while.
Seems the only way to get superior throughput over reasonable distances
with reasonably low RF emissions is fiber optics.  USB, while superior
to RS232, does not have near the performance to act as a system bus.

Peter E. Fry

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<55j9q4$dtf@voyager.iii.org.tw> <32825a4d.6217654@NewsServer.cc.monash.edu.au> <32838f5c.910767@news.escape.ca> <32851A7B.7F5E@ix.netcom.com> <328520E4.215D@lehigh.edu> <32865b6a.585145543@news.zip.com.au> <3286A74E.5656@lehigh.edu> <3286F48B.2829@ocean.com.au> <328ab895.871183655@news.zip.com.au> <328BF96B.27BE@ocean.com.au> <1996Nov15.123714@eos.hitc.com> <328D54D3.5B77@ocean.com.au> <3290D06E.38DB@tiac.net>

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From: "Peter E. Fry" <pfry@cyberramp.net>
Subject: Re: The Jumperless Pentium Mainboard
Date: 1996/11/18
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references: <55j9q4$dtf@voyager.iii.org.tw> <32825a4d.6217654@NewsServer.cc.monash.edu.au> <32838f5c.910767@news.escape.ca> <32851A7B.7F5E@ix.netcom.com> <328520E4.215D@lehigh.edu> <32865b6a.585145543@news.zip.com.au> <3286A74E.5656@lehigh.edu> <3286F48B.2829@ocean.com.au> <328ab895.871183655@news.zip.com.au> <328BF96B.27BE@ocean.com.au> <1996Nov15.123714@eos.hitc.com> <328D54D3.5B77@ocean.com.au> <3290D06E.38DB@tiac.net>
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