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Article #272

Re: P5

#272
From: Nico de Vries.
Date: Fri, 17 Apr 1992 06:30
40 lines
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In <1992Apr17.003646.6201@magnus.acs.ohio-state.edu> adingus@magnus.acs.ohio-state.edu (Aaron T Dingus) writes:

>I have heard that the P5 is capable of exceeding 100 MIPS.
>That is quite a jump from a 486/50's 20 or so.  I have also
It has to be seen. The 486 was faster in the specs than in reality too
(BTW I believe the 486/50 is faster but that is another matter). Most
important is that it will have some superscalar stuf allowing it to
execute multiple instructions in a single clock cycle (not by clock
doubling like the DX2 BTW). It will be faster than the 486.

Intel is in a bit of a hury since the Cyrix and AMD 486 and perhaps
even the TI 586 are coming.

>heard that it uses a special set of registers, and other
>interesting new stuff.
It is supposed to be a nearly excact copy of the 486 in specs, same
registers instructions etc.

>If someone in the know about the capabilites/release date of this
>new processor would like to drop me a line, it would be greatly
>appreciated.
The first proto products should appear in small quantities this year.
Next year in production.

>Thanks.

>-ATD
>-- 
>Aaron T. Dingus


Nico E. de Vries
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Path: arc1-ca.pugleaf.net!sparky!uunet!mcsun!sun4nl!alchemy!accucx!nevries
From: nevries@accucx.cc.ruu.nl (Nico de Vries.)
Newsgroups: comp.sys.intel
Subject: Re: P5
Message-ID: <2428@accucx.cc.ruu.nl>
Date: 17 Apr 92 06:30:15 GMT
References: <1992Apr17.003646.6201@magnus.acs.ohio-state.edu>
Organization: Academic Computer Centre Utrecht
Lines: 40