🚀 go-pugleaf

In article <Bt0AKM.4zz@pix.com> hsu@pix.com (Dagwood Splits the Atom) writes:

>All is not lost, though.  The 860's floating point unit is widely rumored
>to have been adapted for the P5 (egads...an x86 with enough guts to do
>some serious DSP!).

At Hot Chips was given an architectural description of the P5's floating
point unit.  It is *possible* that it was derived from the i860s;
certainly it is a mostly-hardware FPU, and possibly some work was brought over
(nothing to this effect was said at the conference).

On the other hand:

The i860 executes RISC-like operations (i.e., no sin. cos, etc), usng
64-bit registers, of which there are certainly more than 8, arranged as
a regular register file.

The P5 does the X86 FP set (including sin, cos, etc) using 80-bit
registers, of which there are 8, arranged in a stack, and whose design
goes to great lengths to parallel-handle an operation that
normally leaves reslt on top of stack together with an FXCHG that
moves the result somewhere else, i.e., to avoid the stack-top
bottleneck.

Perhaps, underneath, some circuits were brought over, but on the surface,
the 2 FPUs sound about *as different as they could be* and still be little-
endian CPUs that do IEEE floating point...
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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