Article View: comp.sys.intel
Article #513Re: Help - Cyrix processors, anyone know for sure?
From: Charles Clark
Date: Sun, 23 Aug 1992 05:54
Date: Sun, 23 Aug 1992 05:54
17 lines
1319 bytes
1319 bytes
In article <1992Aug21.170154.23076@tandon.com> tdbear@tandon.com (Tom Barrett) writes: > >The external cache controller doesn't need to be aware of the >Cyrix internal cache because they did something smart... as >long as the 386 socket has a real HOLD signal going to it, the >Cyrix can be programmed to flush it's internal write-through >cache on each DMA. All this talk of flushing, I've got to ask... Why aren't cache line invalidations used? Obviously, something is missing or they wouldn't resort to flushing the entire cache... What is it about 386 based systems that make this impossible? Thanks, --Charles
Technical Details
Message-ID:
<1992Aug22.235448.28070@hellgate.utah.edu>Path:
arc1-ca.pugleaf.net!sparky!uunet!cs.utexas.edu!hellgate.utah.edu!asylum.cs.utah.edu!clarkReferences:
<1992Aug13.215958.4016@bcars64a.bnr.ca> <Bt91A8.212@nntp-sc.Intel.COM> <1992Aug21.170154.23076@tandon.com>Show Full Headers
Complete Article Headers
Newsgroups: comp.sys.intel,comp.sys.ibm.pc.hardware Path: arc1-ca.pugleaf.net!sparky!uunet!cs.utexas.edu!hellgate.utah.edu!asylum.cs.utah.edu!clark From: clark%asylum.cs.utah.edu@cs.utah.edu (Charles Clark) Subject: Re: Help - Cyrix processors, anyone know for sure? Date: 22 Aug 92 23:54:48 MDT Message-ID: <1992Aug22.235448.28070@hellgate.utah.edu> Followup-To: comp.sys.ibm.pc.hardware,comp.sys.intel Summary: Cache invalidation cycles? Keywords: Intel, P5, Cyrix, 486DLC, i386, Gomez Sender: clark@cs.utah.edu Organization: University of Utah, CS Dept References: <1992Aug13.215958.4016@bcars64a.bnr.ca> <Bt91A8.212@nntp-sc.Intel.COM> <1992Aug21.170154.23076@tandon.com> Lines: 17