🚀 go-pugleaf

In article <0105010F.bsia3c@mprnews.mpr.com>, mslater@mpr.com (Michael Slater) writes:

| for the write-back cache. Intel has defined a new OverDrive
| socket, which it recommends for DX2 systems, that has an extra
| row of pins surrounding the standard OverDrive socket. Most of
| these pins are power and ground; six of them are being
| documented only for customers who sign non-disclosure
| agreements (these are the write-back cache support pins).

  Just a note, I was unable to get Intel to send me such an agreement,
or even get them to admit they would do such a thing. They appear to be
claiming that this is only done for customers who make systems for
retail resale, and is not available to customers who want to embed x86
systems in commercial products, or use them inhouse. The sales 'droid
had been trained to ask "Do you manufacture motherboards for resale to
other vendors or end users?" and if the answer was no to say "that
information is not available to end users at this time."

  Since the P5 is not currently deliverable, it turned out that
performance was not in any way an issue after all.

-- 
bill davidsen, GE Corp. R&D Center; Box 8; Schenectady NY 12345
    I admit that when I was in school I wrote COBOL. But I didn't compile.