🚀 go-pugleaf

>>>
* dbarber@crash.cts.com (David C. Barber) Has heretofor espoused:
*
>In <1992Oct22.054643.27802@exucom.com> cyberman@exucom.com (Stephen R. Phillips) writes:
>
>>Thier I860 chipset uses seperate chaches.
>>They may have a problem with the using I and D caches since with a
>>CISC processor thing get more convoluted :)
>
>>Cyberman/Stephen
>
>You are right about seperate I & D caches being a problem on many
>CISC machines.  You didn't give the main reason though:  CISC machines
>(like x86 series) can dynamically programatically alter their code by
>way of data writes that have to be able to find their way into the
>instruction cache.
>


This was in fact, (and still is ) a method of copy protection used on the
x86s

	if you have:

1000:	mov bx,1008
1004	inc [bx]
1008:	jmp label
....

2000:label

Or something similar, you trash the memory (as viewed by a debugger) 
whereas the pre-fetch queue (not really a cache, but this is what you're 
talking about) will have the correct data, when executing, but not in the 
debugger. Anyone stepping through the code will die a horrible flaming death. 

It's kinda useful if you want to alternate between N jump dests in a loop
Not really reccommended coding practice, it's fast small, and if you're working
with me, had better damn well be commented :)


					-mikey
-- 

|mikey@cs.mcgill.ca           -Mike Gallop-      	      McGill Comp Sci |
|	               	Life is Short, Play Hard			      |