🚀 go-pugleaf

In article <TMH.92Aug26230950@doppel.first.gmd.de> tmh@doppel.first.gmd.de (Thomas Hoberg) writes:
>In article <BtLGIG.3q2@pgroup.com> I write:
>   Actually, the announcement was that Intel had admitted the failure of
>   the i860 as a general-purpose CPU.  They still intend to support it in
>   graphics and embedded applications; speculation is that they will also
>   support it for the iPSC MPP systems.  No followon has been announced,
>   but one would obviously be needed if they do indeed plan to continue to
>   use i860-like chips in the iPSC.
>

One reason why the i860(tm) did do better may be that good compilers
were not available when it was first introduced. It would have been
better for the i860 if they had developed compilers while designing
the chip. The compilers have improved, but it may be too late.

Of all the modern micros, the i860(tm) is the  only one I know of
that allows one to bypass cache. There are two instructions to
laod floating point registers; a normal load which will fetch 
from cache if there is a hit and load a line of cache if there is 
a miss; the second, a pipelined load, will fetch from cache if 
there is a hit and from main memory without updating cache if 
there is a miss. If data is in cache, normal loads are faster.
If data will not be reused, pipelined laods may be faster.
Judicious use of these two instructions can
make some numerically intensive code run fast.  
Unfortunately, the compilers do not normally generate the pipelined load 
instructions because of the complexity in deciding whether
whether  data will be reused.  This may be the reason that assembly 
language programmers can get good results (they know the algorithm), 
but compilers do not.  This, I think, is  very important point because
for numerically intensive code, memory bandwidth is very important.




--

King Lee
klee@nas.nasa.gov