Article View: comp.sys.intel
Article #551Re: Future of i860 line
From: Rich Stewart
Date: Mon, 31 Aug 1992 15:16
Date: Mon, 31 Aug 1992 15:16
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1739 bytes
In article <Btr4Iz.GB9@pgroup.com> lfm@pgroup.com (Larry Meadows) writes: >In article <1992Aug29.031847.28867@nas.nasa.gov> klee@wilbur.nas.nasa.gov (King M. Lee) writes: >> >>One reason why the i860(tm) did do better may be that good compilers >>were not available when it was first introduced. It would have been >>better for the i860 if they had developed compilers while designing >>the chip. The compilers have improved, but it may be too late. > >Are you listening, Intel? > >> >>Of all the modern micros, the i860(tm) is the only one I know of >>that allows one to bypass cache. There are two instructions to > >Yes! Very good point. If you can't bypass cache then you have >to hope/arrange for re-use, which is much harder. >-- >Larry Meadows The Portland Group >lfm@pgroup.com Stop this. You can bypass cache on lots of chips. Most caching cpu's can have cache bypassed in the page tables. A second way, if your board is designed to do it, is a software toggle of some sort. I think, most modern cpu's, have a cache enable/disable pin. And finally, you do not want to use pfld's that might access memory that is in a cachable address range. (Right Larry?). -Rich
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Newsgroups: comp.sys.intel Path: arc1-ca.pugleaf.net!sparky!uunet!news.claremont.edu!ucivax!megatek!rstewart From: rstewart@ganglia.megatek.uucp (Rich Stewart) Subject: Re: Future of i860 line Message-ID: <1992Aug31.151640.16824@megatek.com> Sender: rstewart@megatek.com (Rich Stewart) Reply-To: megatek!rstewart@uunet.uu.net Organization: Megatek Corporation, San Diego, California References: <1992Aug28.182116.4396@megatek.com> <1992Aug29.031847.28867@nas.nasa.gov> <Btr4Iz.GB9@pgroup.com> Date: Mon, 31 Aug 1992 15:16:40 GMT Lines: 28