🚀 go-pugleaf

>>Can the 486  on-chip cache maintain cache coherency in 
>>a shared memory MP configuration ? 
>>
>>Al Dykes
>>---------
>>adykes@jpr.com

>   Yes, it has bidirectional address lines.
>   I don't recall, however, if it can implement Exclusive/Shared/Dirty/Invalid
>status on the cache and source its data to other caches, or will only flush
>the cache or a single line when an address in its cache is given to the chip
>from an outside system. 
>-- 
>         -----> All opinions expressed here are my own, not IBM's <-----
>Raul Izahi Lopez	Izahi Engineering
>izahi@bsc.no		IBM Bergen Environmental Sciences and Solutions Centre
>			Thormoehlensgate 55, 5008 Bergen, NORWAY (47-5)54-4653

The 486 has write-through caches, so it only implements the Valid 
(Exclusive/Shared) and Invalid states of the MP MOESI cache protocol.  
(The 486 can't tell the difference between a line that is exclusive 
and shared, since it only has a valid bit.) 

Typically, 486 MP systems will have a second level cache that will take
care of the MP protocol for each 486.  An MP system with write-through cache
CPUs would not perform terribly well, because the of MP bus bandwidth
chewed up by all the writes.

John McBride